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51. 发明专利

AU2749599A A method for generating electrical conducting or semiconducting structures in two or three dimensions, method for erasing the same structures and an electric field generator/modulator for use with the method for generating 未知
公开(公告)号：AU2749599A
公开(公告)日：1999-09-15
申请号：AU2749599
申请日：1999-01-28
申请人： THIN FILM ELECTRONICS ASA
发明人： NORDAL PER-ERIK , LEISTAD GEIRR I , GUDESEN HANS GUDE
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/26 , H01L21/336 , H01L21/64 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L23/52 , H01L27/092 , H01L29/06 , H01L29/786 , H01L29/861 , H01L51/05 , H01L51/40
摘要： A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

52. 发明专利

CA2301283A1 A FERROELECTRIC DATA PROCESSING DEVICE 未知
公开(公告)号：CA2301283A1
公开(公告)日：1999-03-11
申请号：CA2301283
申请日：1998-08-13
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE , LEISTAD GEIRR I , NORDAL PER-ERIK
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/06 , H01L27/105 , H01L27/115 , H03K19/177 , H03K19/185
摘要： In a ferroelectric data-processing device for processing and/or storage of data with active or passive electrical addressing a data-carrying medium are used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched therebetween and is provided as a continuous or patterned layer above and adjacent to electrode structures in the form of a matrix, the electrode structures being mutually isolated by an electrical isolating material (6). A logic element (4) is formed in the thin film (1) along the side edges of an y electrode (3) and down to the x electrode (2) at the overlap. The logic element (4) is addressed by applying to the electrodes (2,3) a voltage greater than the coercivity field of the ferroelectric material. Dependent on the polarization state and the form of the hysteresis loop of the ferroelectric material a distinct detection of the polarization state in the logic element (4) is obtained and it may also be; possible to switch between the polarization states of the logic element, which hence may be used for implementing a bistable switch or a memory cell. The data-processing device according to the invention may be stacked layerwise if the separate layers are separated by an electricalinsulating layer and hence be used for implementing volumetric data-processing devices.

53. 发明专利

CA2353496C SCALABLE DATA PROCESSING APPARATUS 未知
公开(公告)号：CA2353496C
公开(公告)日：2007-11-13
申请号：CA2353496
申请日：1999-12-03
申请人： THIN FILM ELECTRONICS ASA
发明人： NORDAL PER-ERIK , BERGGREN ROLF MAGNUS , LEISTAD GEIRR I , KARLSSON JOHAN ROGER AXEL , GUDESEN HANS GUDE , GUSTAFSSON BENGT GORAN
IPC分类号： G11C13/00 , H01L27/02 , G11C5/00 , H01L25/065 , H01L27/00 , H01L27/10 , H01L49/02
摘要： In a scalable data processing appa-ratus, particularly a data storage appara-tus, one or more thin-film devices which form a substantially planar layer com-prise a plurality of sublayers of thin film. Two or more thin-film devices are pro-vided as an integrated stack of the sub-stantially planar layers which form the thin-film devices, such that the appara-tus thereby forms a stacked configura-tion. Each thin-film device comprises one or more memory areas which form matrix addressable memories and addi-tionally circuit areas which form elec-tronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said in-terfaces being realized with communica-tion and signal lines as well as supporting circuitry for processing extending verti-cally through dedicated interface areas in the thin-film device.

54. 发明专利

DE69837540D1 未知
公开(公告)号：DE69837540D1
公开(公告)日：2007-05-24
申请号：DE69837540
申请日：1998-06-05
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE , LEISTAD GEIRR I , NORDAL PER-ERIK
IPC分类号： G02F3/00 , G02F3/02 , G11C7/00 , G11C11/56 , G11C13/00 , G11C13/02 , G11C13/04
摘要： In a multistable optical logic element with a light-sensitive organic material (1) which undergoes a photocycle with several physical states by irradiation with light, and wherein a physical state is assigned a logical value which can be changed by addressing the element optically, the element initially before the addressing is in a metastable state generated in advance. A multistable optical logic element has been made proximity-addressable by providing at least a color light source (2) for optical addressing and at least one color-sensitive optical detector (5) adjacent to the light-sensitive material. In a method for preparing of the light-sensitive material (1) a desired initial metastable state is generated in the photocycle and assigned a determined logical value for the element. In a method for optical addressing of the optical logic element steps for respectively writing and storing, reading, erasing and switching comprises generating transitions between states in the photocycle and detection of the states. Use in an optical logical device for storing and processing of data.

55. 发明专利

CA2466153C INTEGRATED TRANSISTOR/MEMORY STRUCTURES AND A MATRIX-ADDRESSABLE ARRAY THEREOF 未知
公开(公告)号：CA2466153C
公开(公告)日：2007-01-23
申请号：CA2466153
申请日：2002-11-18
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE
IPC分类号： H01L27/088 , H01L27/105 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8246 , H01L27/00 , H01L27/04 , H01L27/092 , H01L27/10 , H01L27/28 , H01L51/05
摘要： comprises one or more layers (1) of semiconducting material, two or more electrode layers, and memory material (11) contacting electrodes (2,6, 10) i n the latter. At least one layer of a semiconducting material and two electrod e layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes (2;6) of a single transistor/memory structure are separated by a narrow recess (3) extending down to the semiconducting (1) layer wherein the transistor channel (8) is provided beneath the recess and with extremely sma ll width, while the source and drain regions are provided beneath the respectiv e source and drain electrodes (2;6) on either side of the transistor channel(8 ). Memory material (11) is provided in the recess (3) and contacts the electrod es (2,6,10) of the transistor. This arrangement defines the transistor channel (8) with a length L corresponding to the width of the recess (3) and a width W corresponding to the width of the gate electrode (10), L being a fraction of W, and three memory cells in the memory material (11) formed respectively between the source electrode (2) and the gate electrode (10), the drain electrode (6) and the gate electrode (10) and in the recess between the sour ce and drain electrodes (2;6).

56. 发明专利

AT343841T 未知
公开(公告)号：AT343841T
公开(公告)日：2006-11-15
申请号：AT02755997
申请日：2002-08-28
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE , NORDAL PER-ERIK
IPC分类号： G01C11/22 , G11C11/22 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L27/28 , H01L51/05 , C08L27/16

57. 发明专利

DK1364372T3 未知
公开(公告)号：DK1364372T3
公开(公告)日：2006-10-30
申请号：DK02700903
申请日：2002-02-15
申请人： THIN FILM ELECTRONICS ASA
发明人： NORDAL PER-ERIK , GUDESEN HANS GUDE , LEISTAD GEIRR I
IPC分类号： G11C7/12 , G11C8/08 , G11C11/16 , G11C11/22 , G11C11/401
摘要： In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits ( 3; 4 ). An active word line (AWL) is selected by a multiplexer ( 7 ), while inactive word lines (IWL) are clamped to ground during readout. A second apparatus for performing the method is rather similar, but has only a single detection circuit ( 3, 4 ). An active word line (AWL) is selected by multiplexer ( 7 ) and a bit line (ABL) is selected by a multiplexer ( 9 ) provided between one end of the bit lines (BL) and the input of the detection circuit ( 3, 4 ), while inactive word and bit lines (IWL; IBL) are clamped to ground during readout.

58. 发明专利

AU2002321949B2 Non-volatile memory device 未知
公开(公告)号：AU2002321949B2
公开(公告)日：2006-09-21
申请号：AU2002321949
申请日：2002-08-28
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE , NORDAL PER-ERIK
IPC分类号： G01C11/22 , G11C11/22 , C08L27/16 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L27/28 , H01L51/05

59. 发明专利

NO322202B1 未知
公开(公告)号：NO322202B1
公开(公告)日：2006-08-28
申请号：NO20045727
申请日：2004-12-30
申请人： THIN FILM ELECTRONICS ASA
发明人： GUDESEN HANS GUDE , HAGEL OLLE , DYREKLEV PETER , NORDAL PER-ERIK , HAGERSTROM ANDERS
IPC分类号： H01L21/56 , G11C11/22 , H01L20060101 , H01L21/30 , H01L21/48 , H01L21/50 , H01L27/115 , H01L51/40
摘要： In a method for fabricating a memory device based on an electrically polarizable memory material in the form of an electret or ferroelectric material, the memory device comprises one or more layers with circuit structures provided exclusively or partially in a printing process. At least one protective interlayer is provided between at least two layers in the memory device, said protective interlayer exhibiting low solubility as well as low permeability for any solvents employed in the deposition of the other layers in the device. Use in fabricating a memory device, particularly a passive matrix-addressable memory device with an electret or ferroelectric memory material.

60. 发明专利

NO20050967L 未知
公开(公告)号：NO20050967L
公开(公告)日：2006-08-24
申请号：NO20050967
申请日：2005-02-23
申请人： THIN FILM ELECTRONICS ASA
发明人： GUSTAFSSON GORAN , GUDESEN HANS GUDE , DYREKLEV PETER , NORDAL PER-ERIK , ENGQUIST ISAK
IPC分类号： G11C11/56 , G11C11/22 , H01L20060101 , H01L27/10

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