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51. 发明申请

US20090289341A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090289341A1
公开(公告)日：2009-11-26
申请号：US12468284
申请日：2009-05-19
申请人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
发明人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
IPC分类号： H01L23/02
CPC分类号： G06K19/07749 , G06K19/07735 , H01L27/1214 , H01L27/1218 , H01L27/1266 , H01L27/13 , H01Q1/38 , H01Q7/00
摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.
摘要翻译：目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽提供第二绝缘体的表面。设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

52. 发明授权

US07596024B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07596024B2
公开(公告)日：2009-09-29
申请号：US11776973
申请日：2007-07-12
申请人： Kiyoshi Kato , Shunpei Yamazaki
发明人： Kiyoshi Kato , Shunpei Yamazaki
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/12 , G11C8/14 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/12 , H01L27/124
摘要： A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.
摘要翻译：高度集成的非易失性存储器。存储单元阵列，其中多个存储单元以行和列方向排列成矩阵，多个第一和第二字线以及多个位线。多个存储单元中的每一个包括串联连接的第一存储晶体管和第二存储晶体管。第一存储晶体管的栅电极连接到第一字线，第二存储晶体管的栅电极连接到第二字线，第一存储晶体管的源极和漏极区之一连接到第一位线并且第二存储晶体管的源极和漏极区中的一个连接到第二位线。第一位线和第二位线中的每一个被共同地设置在彼此相邻的列中的存储器单元。

53. 发明授权

US07583250B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07583250B2
公开(公告)日：2009-09-01
申请号：US10793822
申请日：2004-03-08
申请人： Kiyoshi Kato , Toshihiko Saito
发明人： Kiyoshi Kato , Toshihiko Saito
IPC分类号： G09G3/36
CPC分类号： G02F1/13338 , G02F1/13306 , G02F1/133305 , G02F1/133345 , G02F1/13439 , G02F1/13454 , G02F1/136213 , G02F1/1368 , G02F2201/123 , G06F3/0412 , G06F3/044 , G09G3/36 , H01L27/12 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/1255 , H01L27/1288 , H01L27/13 , H01L27/3244 , H01L29/78621 , H01L29/78645
摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.
摘要翻译：可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

54. 发明申请

US20090216624A1 OPERATIONS MANAGEMENT APPARATUS, OPERATIONS MANAGEMENT SYSTEM, DATA PROCESSING METHOD, AND OPERATIONS MANAGEMENT PROGRAM 有权
标题翻译：操作管理装置，操作管理系统，数据处理方法和操作管理程序
公开(公告)号：US20090216624A1
公开(公告)日：2009-08-27
申请号：US12391445
申请日：2009-02-24
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06Q10/00 , G06F17/10
CPC分类号： G06N5/02 , G06F11/3409 , G06F11/3447 , G06F11/3476 , G06Q10/0639
摘要： An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includesa correlation model generation unit which derives a correlation function between a first element and a second element of the performance information, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, anda model searching unit which searches for the correlation model for each element between an input element and an output element among elements of the performance information in series, and predicts a value of the output element from a value of the input element based on the searched correlation model.
摘要翻译：一种操作管理装置，其从多个受控单位取得多个演奏项目的演奏信息，并管理上述受控单位的动作，包括：相关模型生成部，其将第一，第二组合的相关函数，性能信息，基于相关函数产生第一元素和第二元素之间的相关模型，并获得每个元素对的性能信息的相关模型，以及模型搜索单元，其搜索每个元素之间的相关模型输入元素和输出元素，并且基于搜索到的相关模型从输入元素的值预测输出元素的值。

55. 发明申请

US20090206345A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206345A1
公开(公告)日：2009-08-20
申请号：US12429200
申请日：2009-04-24
申请人： Kiyoshi Kato , Tadafumi Ozaki , Kohei Mutaguchi
发明人： Kiyoshi Kato , Tadafumi Ozaki , Kohei Mutaguchi
IPC分类号： H01L33/00
CPC分类号： H01L29/78621 , H01L27/12 , H01L27/1285 , H01L29/66757 , H01L29/78675
摘要： A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.
摘要翻译：具有尺寸小的显示单元的半导体器件抑制由于将IC芯片等安装在基板上而引起的缺陷，并且高速运转。通过使用实现高移动性的TFT的制造工艺，半导体显示单元和其它电路块一体地形成在具有绝缘表面的基板上。具体地，采用使用连续振荡激光使半导体活性层结晶的工艺。此外，仅依赖于必须以高速运转的电路块选择性地实现依赖于连续振荡激光的结晶工艺，从而实现高生产效率。

56. 发明授权

US07561476B2 Nonvolatile memory, verify method therefor, and semiconductor device using the nonvolatile memory 有权
公开(公告)号：US07561476B2
公开(公告)日：2009-07-14
申请号：US11072198
申请日：2005-03-03
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C16/04
CPC分类号： G11C16/3472 , G11C16/3468 , G11C16/3481
摘要： Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier (102) that performs reading is connected to a switch which switches an operation voltage applied to a memory cell in accordance with a verify signal Sv, and the verify operation is finished concurrently with having the verify signal Sv switched. By obtaining such circuit construction and simultaneously performing writing/erasing and reading, it becomes possible to perform high-speed verify writing/erasing.

57. 发明授权

US07509603B2 Semiconductor integrated circuit and design method thereof 有权
标题翻译：半导体集成电路及其设计方法
公开(公告)号：US07509603B2
公开(公告)日：2009-03-24
申请号：US10595567
申请日：2004-10-25
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5045
摘要： A design method of a logic circuit, capable of shortening the design period, is achieved by this invention. A semiconductor integrated circuit has a plurality of logic blocks each of which is constituted by a first logic circuit and a second logic circuit. Such semiconductor integrated circuit is designed in at least two steps: a first design step in which designing layout and timing verification are performed for a logic circuit including signal lines between the logic blocks and the first logic circuit; and a second design step in which layout and timing verification are performed for the second logic circuit in each logic block independently.
摘要翻译：通过本发明实现了能够缩短设计周期的逻辑电路的设计方法。半导体集成电路具有多个逻辑块，每个逻辑块由第一逻辑电路和第二逻辑电路构成。这样的半导体集成电路至少被设计为两个步骤：第一设计步骤，其中对逻辑电路进行设计布局和定时验证，逻辑电路包括逻辑块和第一逻辑电路之间的信号线; 以及第二设计步骤，其中独立地对每个逻辑块中的第二逻辑电路执行布局和定时验证。

58. 发明申请

US20090071675A1 BATTERY PACK AND CORDLESS TOOL USING THE SAME 有权
标题翻译：电池组和使用它的无缝工具
公开(公告)号：US20090071675A1
公开(公告)日：2009-03-19
申请号：US12280948
申请日：2007-02-28
申请人： Hiroyuki Hanawa , Kiyoshi Kato , Kazuhiko Funabashi , Katsuhiro Oomori
发明人： Hiroyuki Hanawa , Kiyoshi Kato , Kazuhiko Funabashi , Katsuhiro Oomori
IPC分类号： B23B45/02 , H01M2/00
CPC分类号： H01M2/34 , H01M2/1055 , H01M2/204 , H01M10/052 , H01M10/4207 , H01M10/441 , H01M10/482 , H02J7/00 , H02J7/0031
摘要： A battery device is constituting by connecting such cell assemblies in parallel as each comprises: a first cell group having a plurality of cells connected in series; a housing container for housing said first cell group; current detecting means housed in said container for detecting a current to flow through the first cell group; a switching element connected with said first cell group for turning ON/OFF the current to flow through said first cell group; and means for controlling the ON/OFF of said switching element in response to the output signal of said current detecting means.
摘要翻译：通过并联连接这样的电池组件构成电池装置，每个电池组件包括：具有串联连接的多个电池的第一电池组; 用于容纳所述第一电池组的容纳容器; 电流检测装置，容纳在所述容器中，用于检测流过所述第一电池组的电流; 与所述第一单元组连接的开关元件，用于导通/关闭所述电流流过所述第一单元组; 以及用于响应于所述电流检测装置的输出信号控制所述开关元件的ON / OFF的装置。

59. 发明申请

US20080247208A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20080247208A1
公开(公告)日：2008-10-09
申请号：US12051473
申请日：2008-03-19
申请人： Masashi Fujita , Kiyoshi Kato
发明人： Masashi Fujita , Kiyoshi Kato
IPC分类号： H02M7/217
CPC分类号： G06K19/0723 , G06K19/0701
摘要： A semiconductor device is provided, which comprises a rectifier circuit configured to generate a first voltage from a first signal inputted from an input terminal, a comparing circuit configured to compare a reference voltage and the first voltage inputted from the rectifier circuit and to output a second signal to a switch, and a voltage generation circuit configured to generate a second voltage from the first signal inputted from the input terminal. The rectifier circuit includes a transistor including at least a control terminal, and the voltage generation circuit inputs the second voltage to the control terminal when the switch is turned on in accordance with the second signal.
摘要翻译：提供一种半导体器件，其包括：整流电路，被配置为根据从输入端子输入的第一信号产生第一电压;比较电路，被配置为比较参考电压和从整流器电路输入的第一电压，并输出第二电压信号到开关，以及电压产生电路，被配置为根据从输入端子输入的第一信号产生第二电压。整流电路包括至少包括控制端子的晶体管，并且当根据第二信号接通开关时，电压产生电路将第二电压输入到控制端子。

60. 发明申请

US20080093935A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080093935A1
公开(公告)日：2008-04-24
申请号：US11905504
申请日：2007-10-01
申请人： Toshihiko Saito , Yutaka Shionoiri , Kiyoshi Kato
发明人： Toshihiko Saito , Yutaka Shionoiri , Kiyoshi Kato
IPC分类号： H02J17/00
CPC分类号： H01L27/12 , G06K19/0701 , G06K19/0715 , G06K19/0723 , H01L21/84
摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.
摘要翻译：本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD 0，高可以以小的电路面积获得将数据写入存储器所需的电位。

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