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51. 发明授权

US07564107B2 Power semiconductor device including a terminal structure 有权
标题翻译：功率半导体器件包括端子结构
公开(公告)号：US07564107B2
公开(公告)日：2009-07-21
申请号：US10936601
申请日：2004-09-09
申请人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
发明人： Satoshi Yanagisawa , Satoshi Aida , Shigeo Kouzuki , Hironori Yoshioka , Ichiro Omura , Wataru Saito
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/402 , H01L29/41741 , H01L29/7802
摘要： A semiconductor device is disclosed, which comprises a terminal section formed to surround a device active region. The terminal section includes a trench formed in the semiconductor layer, and a filler filled in the trench. A field plate is extended to above the trench from an electrode of the semiconductor element formed in the device active region.
摘要翻译：公开了一种半导体器件，其包括形成为围绕器件有源区域的端子部分。端子部分包括形成在半导体层中的沟槽和填充在沟槽中的填充物。场板从形成在器件有源区域中的半导体元件的电极延伸到沟槽上方。

52. 发明申请

US20070234206A1 Frame Page Displaying Method, Frame Page Displaying Device, and Program 失效
标题翻译：帧页面显示方式，帧页面显示设备和程序
公开(公告)号：US20070234206A1
公开(公告)日：2007-10-04
申请号：US11587895
申请日：2005-04-27
申请人： Shinji Yamabuchi , Takuya Harakawa , Michimasa Uematsu , Shunji Ito , Koji Matsuzawa , Satoshi Aida , Masayuki Nagamachi
发明人： Shinji Yamabuchi , Takuya Harakawa , Michimasa Uematsu , Shunji Ito , Koji Matsuzawa , Satoshi Aida , Masayuki Nagamachi
IPC分类号： G06F15/00
CPC分类号： G09G5/00 , G06F17/30905 , G09G2340/14 , G09G2340/145 , G09G2370/027
摘要： In a state in which an operation screen for operating a frame in a frame page has been displayed, whether a change occurring to a frame in the page different from the currently displayed frame is a change arising from an operation satisfying a condition that is regarded to represent a user's explicit intention to view the different frame or not is judged. If the change is judged by the judgment to be a change arising from an operation satisfying the condition, the display is shifted to a screen showing the page in whole display and notifying the user of the frame to which the change has occurred.
摘要翻译：在已经显示用于操作帧页面中的帧的操作画面的状态下，是否在与当前显示的帧不同的页面中发生的帧变化是由满足被认为是代表用户的显示意图来查看不同的帧是否被判断。如果通过判断判断为由满足条件的操作引起的改变，则将显示转移到显示整个显示页面的屏幕，并通知用户发生了变化的帧。

53. 发明授权

US07259426B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259426B2
公开(公告)日：2007-08-21
申请号：US11094190
申请日：2005-03-31
申请人： Satoshi Aida , Shigeo Kouzuki , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
发明人： Satoshi Aida , Shigeo Kouzuki , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L21/26586 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/66712 , H01L29/7802
摘要： There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode region connected with at least the semiconductor region and a part of the pillar region, a control electrode and an electrode pad connected with the control electrode. The pillar region including a first region of a first conductivity type and a second region of a second conductivity type is not formed under the electrode pad. Also, a method for manufacturing a MISFET is provided.
摘要翻译：提供了一种功率MISFET，其包括第一导电性的半导体区域，第二导电性的半导体基极区域，柱状区域，基极区域上的第一导电性的第一主电极区域，与第二导电性区域连接的第二主电极区域至少半导体区域和一部分柱区域，控制电极和与控制电极连接的电极焊盘。包括第一导电类型的第一区域和第二导电类型的第二区域的柱区域不形成在电极焊盘下面。另外，提供了用于制造MISFET的方法。

54. 发明授权

US07253507B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07253507B2
公开(公告)日：2007-08-07
申请号：US10975356
申请日：2004-10-29
申请人： Shigeo Kouzuki , Satoshi Aida , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
发明人： Shigeo Kouzuki , Satoshi Aida , Satoshi Yanagisawa , Masaru Izumisawa , Hironori Yoshioka
IPC分类号： H01L23/045
CPC分类号： H01L29/7802 , H01L23/49524 , H01L23/49562 , H01L24/05 , H01L24/06 , H01L24/29 , H01L24/31 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/80 , H01L24/83 , H01L24/85 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/1095 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/0603 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/4103 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48095 , H01L2224/48247 , H01L2224/48472 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2224/83801 , H01L2224/84205 , H01L2224/85205 , H01L2924/00011 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2224/83205 , H01L2924/00012
摘要： A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area. A leading-out direction of the conductive member is substantially parallel to the first direction.
摘要翻译：半导体器件包括半导体元件和导电元件。半导体元件具有具有第一和第二主表面的半导体衬底; 形成在半导体衬底的第一主表面上的半导体层; 形成在所述半导体层上的多个沟槽，所述沟槽彼此平行并延伸到第一方向; 填充沟槽的填充材料; 设置在所述半导体层上并与第一主电极电连接的第一电极焊盘; 设置在第二主表面上的第二主电极; 以及设置在所述半导体层上并与控制所述第一主电极和所述第二主电极之间的导通的栅电极连接的栅电极焊盘。导电构件经由第一接触区域连接到第一电极焊盘和栅电极焊盘中的至少一个。导电构件的导出方向基本上平行于第一方向。

55. 发明申请

US20060081903A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060081903A1
公开(公告)日：2006-04-20
申请号：US11249265
申请日：2005-10-14
申请人： Tomoki Inoue , Satoshi Aida , Yasushi Takahashi , Hitoshi Kobayashi
发明人： Tomoki Inoue , Satoshi Aida , Yasushi Takahashi , Hitoshi Kobayashi
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L21/76224 , H01L29/42368 , H01L29/51 , H01L29/515 , H01L29/66348 , H01L29/66734 , H01L29/7397
摘要： An n channel type power MOS field effect transistor has silica particles buried in a bottom portion of a trench and a gate electrode buried in another portion of the trench. The gate electrode is in contact with the silica particles. A gap of the silica particles is not filled with the gate electrode.
摘要翻译： n沟道型功率MOS场效应晶体管具有掩埋在沟槽的底部的二氧化硅颗粒和埋在沟槽的另一部分中的栅电极。栅电极与二氧化硅颗粒接触。二氧化硅颗粒的间隙没有被栅电极填充。

56. 发明申请

US20060049459A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060049459A1
公开(公告)日：2006-03-09
申请号：US11250464
申请日：2005-10-17
申请人： Satoshi Aida , Shigeo Kouzuki , Masaru Izumisawa , Hironori Yoshioka
发明人： Satoshi Aida , Shigeo Kouzuki , Masaru Izumisawa , Hironori Yoshioka
IPC分类号： H01L29/76
CPC分类号： H01L29/7811 , H01L29/402 , H01L29/456 , H01L29/66712 , H01L29/7802 , H01L29/7813
摘要： A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of a first conductivity type formed on a first main surface of the semiconductor substrate, a surface of the drift layer having a first area and a second area which is positioned on an outer periphery of the first area; a cell portion which is formed in the first area of the drift layer and includes a first base layer of a second conductivity type selectively formed in a surface layer of the first area, a source layer of a first conductivity type selectively formed in a surface layer of the first base layer, a first metallic compound which is formed on the surface layer of the first base layer and a surface layer of the source layer in common, and a control electrode which is formed in the first base layer and the source layer via a first insulating film and has a second metallic compound formed on a top surface thereof; a terminating portion which is formed in the second area of the drift layer, alleviates an electric field to maintain a breakdown voltage by extending a depletion layer, and includes a second base layer of a second conductivity type selectively formed in a surface layer in the second area of the drift layer, an impurity diffused layer of a second conductivity type formed in a surface layer of the second base layer, and a third metallic compound which is provided to a surface layer of the impurity diffused layer, an end surface thereof on the terminating portion side being positioned on the cell portion side away from an end surface of the impurity diffused layer on the terminating portion side; a first main electrode formed so as to be in contact with the first metallic compound and the third metallic compound in common; and a second main electrode formed on a second main surface opposite to the first main surface of the semiconductor substrate.
摘要翻译：半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的第一导电类型的漂移层，所述漂移层的表面具有位于所述第一区域的外周上的第一区域和第二区域; 形成在所述漂移层的所述第一区域中并且包括选择性地形成在所述第一区域的表面层中的第二导电类型的第一基底层的单元部分，选择性地形成在表面层中的第一导电类型的源极层的第一基底层，形成在第一基底层的表面层和共同的源极层的表面层的第一金属化合物以及形成在第一基底层和源极层中的控制电极第一绝缘膜，并且在其顶表面上形成有第二金属化合物; 形成在漂移层的第二区域中的端接部分通过延伸耗尽层来减轻电场以维持击穿电压，并且包括选择性地形成在第二导电类型的表面层中的第二导电类型的第二基极层漂移层的面积，形成在第二基底层的表面层中的第二导电类型的杂质扩散层，以及设置在杂质扩散层的表面层上的第三金属化合物，终端部分侧位于所述单元部分侧，远离所述端接部分侧的所述杂质扩散层的端表面; 形成为与第一金属化合物和第三金属化合物相接触的第一主电极; 以及形成在与所述半导体衬底的所述第一主表面相对的第二主表面上的第二主电极。

57. 发明申请

US20050258503A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050258503A1
公开(公告)日：2005-11-24
申请号：US11186838
申请日：2005-07-22
申请人： Kazuya Nakayama , Satoshi Aida , Shigeo Kouzuki , Masaru Izumisawa
发明人： Kazuya Nakayama , Satoshi Aida , Shigeo Kouzuki , Masaru Izumisawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/4232 , H01L29/42364 , H01L29/42376 , H01L29/4933 , H01L29/66712 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.
摘要翻译：根据本发明的实施例的半导体器件具有通过栅极绝缘膜形成在半导体衬底上并具有狭缝部分的栅电极; 形成在栅电极的两个侧面和狭缝部的侧壁处的侧壁膜，并且填充狭缝部分的内部并在狭缝部分正下方覆盖栅极绝缘膜; 以及形成为覆盖栅电极和侧壁膜的层间绝缘膜。

58. 发明授权

US06930352B2 Insulated gate semiconductor device 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US06930352B2
公开(公告)日：2005-08-16
申请号：US10463613
申请日：2003-06-18
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.
摘要翻译：一种绝缘栅半导体器件，包括：控制电极，具有通过栅极绝缘膜形成在第一导电类型的第一半导体层的表面上并且格栅形状的沟槽型结构，所述控制电极具有多个第一控制电极分别与多个第一控制电极部分相交的多个第二控制电极部分和多个第二导电类型的第五半导体层，其设置在第一半导体层的与多个第一控制电极部分接触的界面上的第二控制电极部分，并且连接到第二导电类型的多个第二半导体层中的至少一个，所述第五半导体层的杂质浓度低于多个第二半导体层的杂质浓度。

59. 发明授权

US06849880B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06849880B1
公开(公告)日：2005-02-01
申请号：US10795325
申请日：2004-03-09
申请人： Wataru Saito , Ichiro Omura , Satoshi Aida
发明人： Wataru Saito , Ichiro Omura , Satoshi Aida
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/402 , H01L29/41775 , H01L29/42372 , H01L29/7813
摘要： A power semiconductor device includes second layers of a second conductivity type disposed in a first layer of a first conductivity type. The second layers extend in a depth direction and are arrayed at intervals. Third layers of the second conductivity type are disposed respectively in contact with the second layers. Fourth layers of the first conductivity type are respectively formed in surfaces of the third layers. A gate electrode faces, through a first insulating film, a channel region, which is each of portions of the third layers interposed between the fourth layers and the first layer. An additional electrode is disposed on each of the second layers through a second insulating film, and faces, through each of the second layers, the first main electrode. The additional electrode is electrically connected to the gate electrode.
摘要翻译：功率半导体器件包括设置在第一导电类型的第一层中的第二导电类型的第二层。第二层在深度方向上延伸并且以间隔排列。第二导电类型的第三层分别设置为与第二层接触。第一导电类型的第四层分别形成在第三层的表面中。栅电极通过第一绝缘膜面向通道区域，沟道区域是介于第四层和第一层之间的第三层的每个部分。附加电极通过第二绝缘膜设置在每个第二层上，并且通过每个第二层面向第一主电极。附加电极电连接到栅电极。

60. 发明授权

US5897495A Ultrasonic wave medical treatment apparatus suitable for use under guidance of magnetic resonance imaging 失效
标题翻译：超声波医疗器械适用于磁共振成像引导下使用
公开(公告)号：US5897495A
公开(公告)日：1999-04-27
申请号：US727036
申请日：1996-10-08
申请人： Satoshi Aida , Mariko Shibata , Katsuhiko Fujimoto , Yoshiharu Ishibashi , Takuji Suzuki , Yasutoshi Ishihara , Kazuya Okamoto
发明人： Satoshi Aida , Mariko Shibata , Katsuhiko Fujimoto , Yoshiharu Ishibashi , Takuji Suzuki , Yasutoshi Ishihara , Kazuya Okamoto
IPC分类号： A61B5/055 , A61B18/00 , A61B19/00 , A61F7/00 , A61N7/02 , G01R33/28
CPC分类号： A61N7/022 , A61N7/02 , G01R33/28 , A61B2090/374
摘要： An ultrasonic wave medical treatment apparatus capable of preventing the displacement of the focal point of the ultrasonic waves from the treatment target portion within the patient, eliminating a need for re-positioning of the ultrasonic wave applicator with respect to the patient, and taking MR images to be utilized during the treatment at a high resolution. In this apparatus, the ultrasonic wave applicator can be integrally incorporated within a treatment table for carrying the patient into the MRI gantry for taking the MR images. The surface coil for taking the MR images can be provided on a surface film of a water bag in the ultrasonic wave applicator, or on a body cavity probe on which the ultrasonic transducer is also provided. The mixing rate of the coupling fluid can be adjusted, and the impedance matching between the ultrasonic transducer and the driving circuit can be maintained by minimizing the reflected electric power from the ultrasonic transducer.
摘要翻译：一种超声波医疗处理装置，其能够防止超声波的焦点从患者体内的治疗对象部位移位，消除了超声波施加器相对于患者重新定位的需要，并且取MR图像以高分辨率在治疗期间使用。在该装置中，超声波施加器可以整体地结合在处理台内，用于将病人携带到用于拍摄MR图像的MRI台架中。用于拍摄MR图像的表面线圈可以设置在超声波施加器中的水袋的表面膜上，也可以设置在也设置有超声波换能器的体腔探针上。可以调节耦合流体的混合速率，并且可以通过使来自超声换能器的反射电力最小化来维持超声换能器与驱动电路之间的阻抗匹配。

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