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51. 发明申请

US20100159709A1 MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：掩模图像校正方法，掩模图案检查方法，照相胶片制造方法和半导体器件制造方法
公开(公告)号：US20100159709A1
公开(公告)日：2010-06-24
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

52. 发明授权

US07730445B2 Pattern data verification method for semiconductor device, computer-readable recording medium having pattern data verification program for semiconductor device recorded, and semiconductor device manufacturing method 失效
标题翻译：用于半导体器件的图案数据验证方法，具有用于半导体器件的图案数据验证程序的计算机可读记录介质和半导体器件制造方法
公开(公告)号：US07730445B2
公开(公告)日：2010-06-01
申请号：US11798725
申请日：2007-05-16
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A pattern data verification method for a semiconductor device, including extracting, from design data, design data corresponding to an edge portion of a mask pattern to obtain an edge portion of a pattern on a substrate to be processed, when the pattern is obtained on the substrate to be processed by using at least two masks each having the mask pattern corresponding to the design data, setting allowable errors with respect to the extracted design data and the design data which is not extracted, respectively, calculating a pattern formed on the substrate to be processed by using at least one mask by process simulation, and comparing an error between the pattern calculated by the simulation and the design data with the allowable error set for the design data.
摘要翻译：一种用于半导体器件的图案数据验证方法，包括从设计数据中提取与掩模图案的边缘部分相对应的设计数据，以获得待处理的基板上的图案的边缘部分，通过使用至少两个具有对应于设计数据的掩模图案的掩模来处理的基板，分别设置相对于所提取的设计数据和未提取的设计数据的允许误差，计算在基板上形成的图案，通过过程模拟使用至少一个掩模进行处理，并将由仿真计算的图案与设计数据之间的误差与设计数据的容许误差进行比较。

53. 发明授权

US07600213B2 Pattern data verification method, pattern data creation method, exposure mask manufacturing method, semiconductor device manufacturing method, and computer program product 有权
标题翻译：图案数据验证方法，图案数据生成方法，曝光掩模制造方法，半导体器件制造方法和计算机程序产品
公开(公告)号：US07600213B2
公开(公告)日：2009-10-06
申请号：US11287205
申请日：2005-11-28
申请人： Shigeki Nojima , Akira Hamaguchi
发明人： Shigeki Nojima , Akira Hamaguchi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A pattern data verification method includes preparing exposure data related to a circuit pattern to be formed on a substrate, calculating a characteristic of an image of an exposure pattern on a resist film to be applied on the substrate, the exposure pattern corresponding to the exposure data, calculating a film thickness of the resist film after being developed based on the characteristic of the image of the exposure pattern, and determining whether the exposure data is acceptable or rejectable based on the film thickness of the resist film after being developed.
摘要翻译：模式数据验证方法包括：准备与要在基板上形成的电路图案有关的曝光数据，计算要施加在基板上的抗蚀剂膜上的曝光图案的图像的特性，对应于曝光数据的曝光图案基于曝光图案的图像的特性，计算显影后的抗蚀剂膜的膜厚度，并且基于显影后的抗蚀剂膜的膜厚确定曝光数据是否可接受或可否认。

54. 发明申请

US20080022244A1 Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method 有权
标题翻译：半导体集成电路图案验证方法，光掩模制造方法，半导体集成电路器件制造方法以及用于实现半导体集成电路图案验证方法的程序
公开(公告)号：US20080022244A1
公开(公告)日：2008-01-24
申请号：US11901030
申请日：2007-09-14
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

55. 发明授权

US07278125B2 Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method 有权
标题翻译：半导体集成电路图案验证方法，光掩模制造方法，半导体集成电路器件制造方法以及用于实现半导体集成电路图案验证方法的程序
公开(公告)号：US07278125B2
公开(公告)日：2007-10-02
申请号：US11176181
申请日：2005-07-08
申请人： Shigeki Nojima
发明人： Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G06T7/001 , G03F1/36 , G06F17/5081 , G06T2207/30148
摘要： A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design pattern that is required on the substrate to detect a first difference value, extracting error candidates at which the first difference value is not less than a first predetermined value, comparing pattern shapes at the error candidates to detect a second difference value, combining, into one group, patterns whose second difference values are not more than a second predetermined value, and extracting a predetermined number of patterns from each group and verifying error candidates of the extracted patterns.
摘要翻译：半导体集成电路图案验证方法包括执行模拟，以基于半导体集成电路设计图案获得要在基板上形成的模拟图案，比较基板上所需的模拟图案和设计图案，以检测第一差分值，提取第一差值不小于第一预定值的错误候选，比较错误候选的图案形状以检测第二差值，将第二差值不大于第二预定值，并且从每个组提取预定数量的模式并验证提取的模式的错误候选。

56. 发明授权

US07229721B2 Method for evaluating photo mask and method for manufacturing semiconductor device 失效
标题翻译：评估光掩膜的方法和制造半导体器件的方法
公开(公告)号：US07229721B2
公开(公告)日：2007-06-12
申请号：US10705954
申请日：2003-11-13
申请人： Shoji Mimotogi , Shigeki Nojima , Osamu Ikenaga
发明人： Shoji Mimotogi , Shigeki Nojima , Osamu Ikenaga
IPC分类号： G03F1/00
CPC分类号： G03F7/70625 , G03F1/44 , G03F1/68 , G03F1/78 , G03F7/705
摘要： A method for evaluating a photo mask comprises preparing a photo mask including a unit drawing pattern, finding a dimensional variation relating to the photo mask, the dimensional variation including first and second dimensional variations, the first dimensional variation occurring due to a positional displacement and size mismatch of the unit drawing pattern in the photo mask and the second dimensional variation occurring due to etching and development relating to a manufacturing of the photo mask, estimating a deteriorated amount of an exposure latitude occurring due to the dimensional variation of the photo mask using the dimensional variation and a degree of influence of the dimensional variation for the exposure latitude, and judging quality of the photo mask by comparing the deteriorated amount of the exposure latitude and an allowable deteriorated amount of the exposure latitude.
摘要翻译：一种用于评估光掩模的方法包括制备包括单元绘图图案的光掩模，找到与光掩模相关的尺寸变化，包括第一和第二尺寸变化的尺寸变化，由于位置偏移和尺寸而发生的第一尺寸变化光掩模中的单位绘图图案的不匹配以及由于与光掩模的制造相关的蚀刻和显影而发生的第二尺寸变化，估计由于光掩膜的尺寸变化而产生的曝光宽容度的恶化量，通过比较曝光宽容度的劣化量和曝光宽容度的允许恶化量来判断曝光宽容度的尺寸变化和影响程度，以及判断光掩模的质量。

57. 发明申请

US20070006115A1 Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device 有权
标题翻译：用于验证掩模图案数据的方法，用于制造掩模的方法，掩模图案验证程序以及用于制造半导体器件的方法
公开(公告)号：US20070006115A1
公开(公告)日：2007-01-04
申请号：US11472441
申请日：2006-06-22
申请人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
发明人： Shigeki Nojima , Yoko Oikawa , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36
摘要： A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is prepared. Mask pattern data on a pattern of a mask used in order to produce the design circuit pattern is prepared. A circuit pattern which is to be obtained by processing a film using the pattern of the mask indicated by the mask pattern data is acquired. Circuit data on a circuit realized by at least a first part of the circuit pattern is produced. A circuit mismatch part where the circuit data and a part of the design circuit data which corresponds to the first part of the circuit pattern do not match up is detected.
摘要翻译：一种验证掩模图案数据的方法包括：在设计电路上准备设计电路数据，实现所需的电气操作。制备具有实现半导体衬底上的设计电路的结构的设计电路图案的数据。准备用于产生设计电路图案的掩模图形上的掩模图案数据。获取通过使用由掩模图案数据指示的掩模的图案来处理胶片而获得的电路图案。产生由电路图案的至少第一部分实现的电路上的电路数据。检测与电路图案的第一部分对应的电路数据和设计电路数据的一部分不匹配的电路失配部。

58. 发明授权

US07131106B2 Integrated circuit pattern designing method, exposure mask manufacturing method, exposure mask, and integrated circuit device manufacturing method 有权
标题翻译：集成电路图案设计方法，曝光掩模制造方法，曝光掩模和集成电路器件制造方法
公开(公告)号：US07131106B2
公开(公告)日：2006-10-31
申请号：US10702535
申请日：2003-11-07
申请人： Koji Hashimoto , Shingo Tokutome , Shigeki Nojima
发明人： Koji Hashimoto , Shingo Tokutome , Shigeki Nojima
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G06F17/5009 , G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： There is disclosed a method of designing a pattern of an integrated circuit comprising calculating the window of lithography process on a substrate, the window being calculated at least in partial data of first design data for designing the circuit pattern of integrated circuit, and the window being also calculated in consideration of a specification value of an exposure mask for use in transfer of the circuit pattern, comparing the calculated window of lithography process and the window of lithography process actually required, revising the partial data when the calculated window is smaller than the actually required window, the partial data being revised such that the window of lithography process on the substrate is equal to or larger than the actually required window, and preparing second design data, the second design data being prepared by updating the first design data by using the revised partial data.
摘要翻译：公开了一种设计集成电路图案的方法，包括计算衬底上的光刻处理窗口，该窗口至少在第一设计数据的部分数据中计算，用于设计集成电路的电路图案，窗口为还考虑到用于电路图案的传送的曝光掩模的规格值进行计算，比较计算的光刻工艺窗口和实际需要的光刻工艺窗口，当计算的窗口小于实际的窗口时修改部分数据修改部分数据，使得基板上的光刻处理窗口等于或大于实际需要的窗口，以及准备第二设计数据，第二设计数据是通过使用第二设计数据来更新第一设计数据修改部分数据。

59. 发明申请

US20060190875A1 Pattern extracting system, method for extracting measuring points, method for extracting patterns, and computer program product for extracting patterns 审中-公开
标题翻译：模式提取系统，提取测点的方法，提取模式的方法，以及提取模式的计算机程序产品
公开(公告)号：US20060190875A1
公开(公告)日：2006-08-24
申请号：US11325515
申请日：2006-01-05
申请人： Yukiyasu Arisawa , Osamu Ikenaga , Shigeki Nojima , Shigeru Hasebe
发明人： Yukiyasu Arisawa , Osamu Ikenaga , Shigeki Nojima , Shigeru Hasebe
IPC分类号： G06F17/50
CPC分类号： G03F7/7065 , G03F1/36 , G03F1/68 , G03F1/84
摘要： A pattern extracting system includes a sampler configured to sample test candidate patterns from a circuit pattern, based on a lithographic process tolerance, a space classification module configured to classify the test candidate patterns into space distance groups depending on a space distance to an adjacent pattern, a density classification module configured to classify the test candidate patterns into pattern density groups depending on a surrounding pattern density, and an assessment module configured to assess actual measurements of dimensional errors of the test candidate patterns classified into the space distance groups and the pattern density groups.
摘要翻译：模式提取系统包括：取样器，被配置为基于光刻处理容限从电路图案中取样测试候选图案;空间分类模块，被配置为根据与相邻图案的空间距离将测试候选图案分类为空间距离组; 密度分类模块，其被配置为根据周围图案密度将测试候选图案分类为图案密度组;以及评估模块，其被配置为评估分类为空间距离组和图案密度组的测试候选模式的尺寸误差的实际测量值。

60. 发明授权

US07090949B2 Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权
标题翻译：制造光掩模的方法和制造半导体器件的方法
公开(公告)号：US07090949B2
公开(公告)日：2006-08-15
申请号：US10724738
申请日：2003-12-02
申请人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
发明人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
IPC分类号： G01F9/00
CPC分类号： G03F1/36 , G03F1/68
摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.
摘要翻译：公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸预定条件。

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