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51. 发明申请

US20120286363A1 Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices 失效
标题翻译：场效应晶体管器件的等效氧化物厚度
公开(公告)号：US20120286363A1
公开(公告)日：2012-11-15
申请号：US13556333
申请日：2012-07-24
申请人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L27/088
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.
摘要翻译：场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层，与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

52. 发明申请

US20110291198A1 Scaled Equivalent Oxide Thickness for Field Effect Transistor Devices 有权
标题翻译：场效应晶体管器件的等效氧化物厚度
公开(公告)号：US20110291198A1
公开(公告)日：2011-12-01
申请号：US12788454
申请日：2010-05-27
申请人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.
摘要翻译：一种形成场效应晶体管器件的方法包括在衬底上形成氧化物层，在氧化层上形成电介质层，在电介质层上形成第一TiN层，在第一层上形成金属层，形成第二TiN 去除一部分第一TiN层，金属层和第二TiN层以暴露介电层的一部分，在介电层的暴露部分上形成化学计量的TiN层，第二层 TiN层，加热器件，并在器件上形成多晶硅层。

53. 发明授权

US08941184B2 Low threshold voltage CMOS device 有权
标题翻译：低阈值CMOS器件
公开(公告)号：US08941184B2
公开(公告)日：2015-01-27
申请号：US13327870
申请日：2011-12-16
申请人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Kisik Choi , Vijay Narayanan
IPC分类号： H01L21/70
CPC分类号： H01L21/823842 , H01L21/02178 , H01L21/02192 , H01L21/28079 , H01L21/28088 , H01L21/28229 , H01L21/823807 , H01L21/823857 , H01L29/1054 , H01L29/161 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.
摘要翻译：一种包括NMOS区和PMOS区的半导体器件; 所述NMOS区域具有包括第一高k栅极电介质，第一功函数设定金属和栅电极填充材料的栅极结构; 所述PMOS区域具有包括第二高k栅极电介质，第二功函数设定金属和栅电极填充材料的栅极结构; 其中所述第一栅极电介质不同于所述第二栅极电介质，并且所述第一功函数设定金属与所述第二功函数设定金属不同。还公开了制造半导体器件的方法，其包括栅极最后工艺。

54. 发明授权

US08716813B2 Scaled equivalent oxide thickness for field effect transistor devices 失效
标题翻译：场效应晶体管器件的等效氧化物厚度变化
公开(公告)号：US08716813B2
公开(公告)日：2014-05-06
申请号：US13556333
申请日：2012-07-24
申请人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/02164 , H01L21/02697 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/518
摘要： A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.
摘要翻译：场效应晶体管器件包括：第一栅堆叠部分，包括设置在衬底上的电介质层，设置在电介质层上的第一TiN层，设置在电介质层上的金属层和设置在金属层上的第二TiN层，与第一栅叠层部相邻设置的第一源极区域和与第一栅极堆叠部分相邻设置的第一漏极区域。

55. 发明申请

US20110207280A1 SCAVANGING METAL STACK FOR A HIGH-K GATE DIELECTRIC 有权
标题翻译：用于高K栅介质的SCAVANGING金属叠层
公开(公告)号：US20110207280A1
公开(公告)日：2011-08-25
申请号：US13099790
申请日：2011-05-03
申请人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
发明人： Takashi Ando , Changhwan Choi , Martin M. Frank , Vijay Narayanan
IPC分类号： H01L21/336
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy→2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.
摘要翻译：高k栅极电介质和金属栅极结构的堆叠包括下部金属层，清除金属层和上部金属层。清除金属层满足以下两个标准：1）反应Si + 2 / y MxOy→2x / y M + SiO2的吉布斯自由能变化为正的金属（M）2）具有更负的金属每个氧原子吉布斯自由能用于形成氧化物，而不是下金属层的材料和上金属层的材料。符合这些标准的清除金属层随着氧原子通过栅电极向高k栅极电介质扩散而捕获氧原子。此外，清除金属层远远地降低了高k电介质下面的氧化硅界面层的厚度。结果，即使在CMOS积分期间的高温处理之后，总栅极电介质的等效氧化物厚度（EOT）减小，并且场效应晶体管保持恒定的阈值电压。

56. 发明申请

US20090108294A1 SCALABLE HIGH-K DIELECTRIC GATE STACK 审中-公开
标题翻译：可调高K电介质盖板
公开(公告)号：US20090108294A1
公开(公告)日：2009-04-30
申请号：US11928391
申请日：2007-10-30
申请人： Changhwan Choi , Takashi Ando , Kisik Choi , Vijay Narayanan
发明人： Changhwan Choi , Takashi Ando , Kisik Choi , Vijay Narayanan
IPC分类号： H01L27/088 , H01L29/78 , H01L21/28 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/28185 , H01L21/823857 , H01L21/823864 , H01L29/517 , H01L29/66545
摘要： A stack comprising a dielectric interface layer, a high-k gate dielectric layer, a group IIA/IIIB element layer is formed in that order on a semiconductor substrate. A metal aluminum nitride layer and, optionally, a semiconductor layer are formed on the stack. The stack is annealed at a raised temperature, e.g., at about 1,000° C. so that the materials in the stack are mixed to form a mixed high-k gate dielectric layer. The mixed high-k gate dielectric layer is doped with a group IIA/IIIB element and aluminum, and has a lower effective oxide thickness (EOT) than a conventional gate stack containing no aluminum. The inventive mixed high-k gate dielectric layer is amenable to EOT scaling due to the absence of a dielectric interface layer, which is caused by scavenging, i.e. consumption of any dielectric interface layer, by the IIA/IIB elements and aluminum.
摘要翻译：在半导体衬底上依次形成包括电介质界面层，高k栅极电介质层，IIA / IIIB族元素层的叠层。在叠层上形成金属氮化铝层和任选的半导体层。堆叠在升高的温度例如约1000℃下退火，使得堆叠中的材料被混合以形成混合的高k栅极电介质层。混合的高k栅极电介质层掺杂有IIA / IIIB族元素和铝，并且具有比不含铝的常规栅极叠层更低的有效氧化物厚度（EOT）。本发明的混合高k栅极电介质层由于不存在由IIA / IIB元素和铝的清除即任何介电界面层的消耗而引起的电介质界面层，因此易于进行EOT缩放。

57. 发明授权

US08753936B2 Changing effective work function using ion implantation during dual work function metal gate integration 有权
标题翻译：在双功能金属门集成中，使用离子注入来改变有效的功函数
公开(公告)号：US08753936B2
公开(公告)日：2014-06-17
申请号：US12190220
申请日：2008-08-12
申请人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Martin M. Frank , Herbert L. Ho , Mark J. Hurley , Rashmi Jha , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L29/49 , H01L21/28079 , H01L21/28088 , H01L21/823842 , H01L27/092 , H01L29/4958 , H01L29/517
摘要： Ion implantation to change an effective work function for dual work function metal gate integration is presented. One method may include forming a high dielectric constant (high-k) layer over a first-type field effect transistor (FET) region and a second-type FET region; forming a metal layer having a first effective work function compatible for a first-type FET over the first-type FET region and the second-type FET region; and changing the first effective work function to a second, different effective work function over the second-type FET region by implanting a species into the metal layer over the second-type FET region.
摘要翻译：提出了离子注入来改变双功能金属栅极整合的有效功函数。一种方法可以包括在第一类型场效应晶体管（FET）区域和第二类型FET区域上形成高介电常数（高k）层; 在第一型FET区域和第二类型FET区域上形成具有与第一型FET兼容的第一有效功函数的金属层; 以及通过在第二类型FET区域上将金属注入到金属层中，将第一有效功函数改变为第二类不同的有效功函数。

58. 发明授权

US08680623B2 Techniques for enabling multiple Vt devices using high-K metal gate stacks 有权
标题翻译：使用高K金属栅极堆叠实现多个Vt器件的技术
公开(公告)号：US08680623B2
公开(公告)日：2014-03-25
申请号：US13433815
申请日：2012-03-29
申请人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
发明人： Martin M. Frank , Arvind Kumar , Vijay Narayanan , Vamsi K. Paruchuri , Jeffrey Sleight
IPC分类号： H01L21/8244 , H01L21/70
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1108
摘要： Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.
摘要翻译：提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压，SRAM nFET和SRAM pFET。

59. 发明授权

US08658501B2 Method and apparatus for flatband voltage tuning of high-k field effect transistors 有权
标题翻译：用于高k场效应晶体管的平带电压调谐的方法和装置
公开(公告)号：US08658501B2
公开(公告)日：2014-02-25
申请号：US12535383
申请日：2009-08-04
申请人： Supratik Guha , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Supratik Guha , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L21/28194 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： In one embodiment, the invention is a method and apparatus for flatband voltage tuning of high-k field effect transistors. One embodiment of a field effect transistor includes a substrate, a high-k dielectric layer deposited on the substrate, a gate electrode deposited on the high-k dielectric layer, and a dipole layer positioned between the substrate and the gate electrode, for shifting the threshold voltage of the field effect transistor.
摘要翻译：在一个实施例中，本发明是用于高k场效应晶体管的平带电压调谐的方法和装置。场效应晶体管的一个实施例包括衬底，沉积在衬底上的高k电介质层，沉积在高k电介质层上的栅电极和位于衬底和栅电极之间的偶极子层，用于使场效应晶体管的阈值电压。

60. 发明申请

US20120270385A1 SWITCHING DEVICE HAVING A MOLYBDENUM OXYNITRIDE METAL GATE 有权
标题翻译：具有氧化亚铁金属栅的切换装置
公开(公告)号：US20120270385A1
公开(公告)日：2012-10-25
申请号：US13536366
申请日：2012-06-28
申请人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Richard A. Haight , Vijay Narayanan , Martin P. O'Boyle , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Richard A. Haight , Vijay Narayanan , Martin P. O'Boyle , Vamsi K. Paruchuri
IPC分类号： H01L21/28
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/51
摘要： A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
摘要翻译：场效应晶体管（FET）包括至少部分地设置在身体区域中的体区和源区。 FET还包括至少部分地设置在体区中的漏极区域和氮氧化钼（MoNO）栅极。 FET还包括具有高介电常数（k）的电介质，其布置在体区和MoNO门之间。

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