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    • 51. 发明授权
    • Sense amplifier circuit
    • 感应放大电路
    • US5305272A
    • 1994-04-19
    • US111738
    • 1993-08-25
    • Kenji MatsuoYasukazu NoineKazuhiko KasaiYoshihiro KatoKazuaki Umetsu
    • Kenji MatsuoYasukazu NoineKazuhiko KasaiYoshihiro KatoKazuaki Umetsu
    • G11C7/06G11C7/10G11C11/419G11C7/00
    • G11C7/1048G11C11/419G11C7/062
    • In a sense amplifier circuit, an output potential is set in a data output state when an operation of the sense amplifier is a worst pass before the start of read access. In a memory read mode, when data corresponding to the worst-pass operation of the sense amplifier circuit is read out, the circuit is previously set in a corresponding data output state. A time delay (gate delay) by a gate does not occur. In contrast, when data corresponding to the best-pass operation of the sense amplifier circuit is read out, the gate delay occurs by this operation. The gate delay, however, is shorter than that of the worst pass. As a result, only the best pass is present as the operation mode of the sense amplifier circuit. Therefore, a high operation speed is achieved, so that a high read speed of the entire memory is achieved.
    • 在读出放大器电路中,当在读取访问开始之前读出放大器的操作是最差通过时,输出电位被设置在数据输出状态。 在存储器读取模式中,当读出对应于读出放大器电路的最差通过操作的数据时,电路被预先设置为相应的数据输出状态。 不会发生门的延时(门延迟)。 相反,当读出对应于读出放大器电路的最佳通过操作的数据时,通过该操作发生门延迟。 然而,门延迟比最差通过时更短。 结果,仅存在最佳通过作为读出放大器电路的操作模式。 因此,实现了高的运行速度,从而实现了整个存储器的高读取速度。