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51. 发明专利

JPH0660674A NONVOLATILE SEMICONDUCTOR STORAGE 失效
公开(公告)号：JPH0660674A
公开(公告)日：1994-03-04
申请号：JP13200693
申请日：1993-06-02
申请人： TOSHIBA CORP
发明人： YAMAMURA TOSHIO , NAKAI HIROTO , ASANO MASAMICHI , KATO HIDEO , TOKUSHIGE KAORU
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115
摘要： PURPOSE:To shorten an entire writing time by writing a nonvolatile storage cell necessary to be rewritten as a result of verify in a long writing time. CONSTITUTION:All storage cells connected to one word line are simultaneously written. In this case, data to be written are 1, 0,..., 0,...1 from a left column of the cell. Accordingly, memory cells of second, third columns are written (positively shifting a threshold value). Then, verifing (reading) is executed. Here, whether a threshold value is larger than a predetermined voltage Vt0min or not is judged. When the threshold value is high at the time of writing, it is passed, while when it is low, it is failed at the time of insufficient writing, and a failure bit is rewritten. A shifting width of the threshold value is decided according to a writing pulse width, and the shorter the failure bit is, the smaller the shift width becomes. A short write pulse is added plural times to converge the threshold value of the cell to a narrow distribution. Here, the writing pulse width is increased to second, third times.

52. 发明专利

JPH02110980A NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02110980A
公开(公告)日：1990-04-24
申请号：JP26316688
申请日：1988-10-19
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： SHOJI ATSUSHI , INAMI MICHIHARU , ASANO MASAMICHI , MIYAGAWA TADASHI , TAURA TADAYUKI
IPC分类号： H01L21/8247 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a memory device which is not only excellent in integration, reliability, and a high speed operation but also electrically erasable by a method wherein an offset transistor is provided, cell transistors adjacent to each other in a widthwise direction of a channel region are isolated from each other through an element isolating region formed self-aligned with a floating gate or a control gate and other processes are performed. CONSTITUTION:A floating gate 6 is made to face toward the surface of a semiconductor substrate 1 through the intermediary of a first gate insulating film 5 and is shorter than the channel length of a channel region, an offset section is provided to one side of a part near a source/drain region 2 on the channel region where the floating gate 6 is not provided, and a control gate 8 is provided to the offset section through the intermediary of a second gate insulating film 7 facing a part of the channel region. And, cell transistors adjacent to each other in a widthwise direction of the channel region are possessed of a drain region and a source region 2 in common respectively and isolated from each other through an element isolating region 3 formed self-aligned with the floating gate 6 or the control gate 8, and the control gate 8 is made to intersect the source/drain region 2 at a right angle.

53. 发明专利

JPH0254500A SEMICONDUCTOR MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0254500A
公开(公告)日：1990-02-23
申请号：JP20480288
申请日：1988-08-19
申请人： TOSHIBA CORP
发明人： NARUGE YASUO , MOCHIZUKI TORU , IWASE TAIRA , ASANO MASAMICHI
IPC分类号： G11C17/00 , G11C17/12 , G11C17/14 , G11C29/00 , G11C29/04
摘要： PURPOSE:To easily remedy a defective chip and to improve the productivity by blowing a fuse with a current flowing through an FET when an FET enters a secondary breakdown state and performing writing operation. CONSTITUTION:When the data is written, namely, when the fuse 7 is blown, a program signal enters and L state to turn off an NMOS 21, thereby applying a source voltage to a word line 11 connected to a memory cell 1 including the fuse 7 to be blown out. Consequently, the NMOS 5 of the memory cell 1 enters the secondary breakdown state and a large current flows in the order of a pad 19, a write data line 17, the fuse 7, the NMOS 5, and the ground. The fuse 7 is blown out and the series connection point between the NMOS 3 and 5 of the selected memory cell 1 and a data write line 17 are disconnected electrically to perform the writing operation.

54. 发明专利

JPH0250398A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0250398A
公开(公告)日：1990-02-20
申请号：JP20133188
申请日：1988-08-12
申请人： TOSHIBA CORP
发明人： TAURA TADAYUKI , ASANO MASAMICHI , YOKOYAMA SADAYUKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/16
摘要： PURPOSE:To prevent erroneous erasing and to improve reliability by dividing a memory cell array into plural blocks, providing common and individual erasing lines at every block, and impressing a prescribed voltage only to the erasing line of the selected block at the time of data writing. CONSTITUTION:For an erasing gate at the time of the data writing, 5V is selectively impressed to only any one of block memory cell arrays 42-1 to 42-k including a selective memory cell, and the other erasing lines are not selected to be 0V. Further, at the time of the erasing, a boosting potential HE is outputted from an erasing boosting circuit 39, the boosting potential HE is outputted, and inputted to erasing gate decoders 43-1 to 43-k. At such a time, all the erasing gate decoders 43-1 to 43-k are selected, erasing lines EL1 to ELk are all made into the boosting potential HE, and all bits are erased in a lump. At such a time, word lines WL1-1 to WLk-l and data lines DL1 to DLn are all set at 0V. Thus, the malfunction of the memory cell at the time of the writing is prevented, and the reliability is increased.

55. 发明专利

JPH01196794A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01196794A
公开(公告)日：1989-08-08
申请号：JP2031388
申请日：1988-01-30
申请人： TOSHIBA CORP
发明人： KATO HIDEO , ASANO MASAMICHI , IWAHASHI HIROSHI
IPC分类号： G11C17/00 , G11C16/04
摘要： PURPOSE:To prevent the deterioration of the yield of a E PROM due to various defects at the time of a production by forming a storing unit for bit data by plural non-volatile transistors (TR) which are not adjacent. CONSTITUTION:In the byte cell array BCA of the E PROM, memory cells MC1-MC16 constituting one unit by 16 are disposed and the respective cells are constituted of the floating gate TR1 of a memory element, a selecting TR2 and a control gate TR3 or the like. Them for instance, the two memory cells MC1 and MC9 or the like disposed at the interval of 7 constitute the one storing unit for the bit data and it is connected to data lines DL1, DL2. Then, the storing unit is formed by the TR1 which is not adjacent to prevent the deterioration in the yield of the E PROM due to the various defects at the time of the production.

56. 发明专利

JPH01173494A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01173494A
公开(公告)日：1989-07-10
申请号：JP33471287
申请日：1987-12-28
申请人： TOSHIBA CORP
发明人： MIYAGAWA TADASHI , YOKOYAMA SADAYUKI , ASANO MASAMICHI
IPC分类号： G11C29/00 , G11C16/06 , G11C17/00 , G11C29/12
摘要： PURPOSE:To attain high-speed writing by changing a voltage to impress from a bias circuit to a gate electrode between at the time of program verifying and at the time of information reading. CONSTITUTION:A gate electrode having the capacity coupling between the floating gate electrode of a memory cell is provided. Further, the respective different voltages are impressed to the gate electrode at the time of the program verifying (a program mode) and at the time of the information reading (a reading mode), a threshold voltage VTH of the apparent memory cell is changed, and a writing margin is obtained. Thus, by changing the threshold voltage VTH of the apparent memory cell, a supply voltage at the respective modes is made constant, and the high-speed writing action to obtain a sufficient writing quantity is attained.

57. 发明专利

JPS6433798A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6433798A
公开(公告)日：1989-02-03
申请号：JP18943687
申请日：1987-07-29
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG
发明人： IMAI MIZUHO , IWAHASHI HIROSHI , ASANO MASAMICHI , MINAGAWA EISHIN , TATSUMI YUICHI
IPC分类号： G11C17/00 , G11C16/06
摘要： PURPOSE:To prevent the generation of a latch-up and the enlargement of a chip by discharging the output node of a CMOS circuit in a condition in which the conductive resistance of a MOS transistor for separation is high after a period to output a higher voltage than a first voltage, and thereafter, lowering the conductive resistance with a control signal. CONSTITUTION:A CMOS circuit 6 is operated by a voltage VC, and it sets an output node 1 to the voltage VC or to a voltage VS. On the other hand, the circuit impresses voltage HV 1 or HV 2, which is higher than the voltage VC, to a node 16 or 15 respectively, boosts them, and takes out the output voltage from an output line COLi. Here, the output of the CMOS circuit 6 is controlled by an inverter 11 between the voltages VC and VS, and given through an output mode 12 to a MOS transistor TR 13. A control signal S3 is applied to the TR 13, and a second voltage, which is higher than the voltage VC, discharges through the node 12 in a condition of a high conductive resistance after the output period. Thereafter, the second voltage is conducted to the MOSTR for separation by the control signal S3, and discharged. Thus, the generation of the latch-up is prevented, and the enlargement of the chip of an integrated circuit is evaded.

58. 发明专利

JPS63306670A MANUFACTURE OF SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS63306670A
公开(公告)日：1988-12-14
申请号：JP14139587
申请日：1987-06-08
申请人： TOSHIBA CORP
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI
IPC分类号： H01L21/8247 , H01L27/10 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PURPOSE:To form the floating electrode and the control gate electrode of a self-transistor in a self-alignment manner by etching a first polysilicon layer and a second polysilicon layer by the same pattern. CONSTITUTION:A field oxide film 25 and a first polysilicon layer 26 are formed on a semiconductor substrate 11. Then, with a pattern 27 as a mask an opening 26a is formed. Then, a second polysilicon layer 28 is formed. Thereafter, with a photoresist pattern 29 as a mask the layer 28 is etched. Subsequently, with a photoresist pattern 30 as a mask the layers 28, 26, etc., are selectively removed. In this case, electrodes are formed by the pattern 30 in a self-aligning manner. Then, a contact hole 33 and an aluminum layer 34 are formed.

59. 发明专利

JPS63268196A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63268196A
公开(公告)日：1988-11-04
申请号：JP10141987
申请日：1987-04-24
申请人： TOSHIBA CORP , TOSHIBA MICRO CUMPUTER ENG , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , IWAHASHI HIROSHI , ASANO MASAMICHI , KIKUCHI SHINICHI , NARITA AKIRA
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
摘要： PURPOSE:To obtain an integrated circuit provided with a sub-boosting circuit having of a high boosting efficiency by setting the absolute value of the threshold voltage of a first MOS transistor TR lower than the threshold voltage of a second MOSTR, and obtaining a boosted output from the output terminal of a selection circuit. CONSTITUTION:A boosted output VPP from a main boosting circuit 11 is supplied to the sub-boosting circuit 12 and a circuit 13 to be supplied. The circuit 12 consists of N-channel type MOSTRs Q1, Q2 and a MOST capacitor C1, and the gates are connected to the selection circuit 14. To the source of the TR Q1, the drain and the gate of the TR Q2 are connected, and to the source of the TR Q2, a node N1 is connected. To the connection point of the source of the TR Q1 and the drain and the gate of the TR Q2, one electrode of the capacitor C1 is connected, but to the other electrode of the C1, a clock pulse phiC from a clock generation circuit 15 is supplied. The circuit 13 comprises an N-channel type MOSTR Q3, and to the drain of the TR Q3, the output terminal of the circuit 11 is connected. By setting the absolute value of the threshold voltage of the TR Q1 lower than the threshold voltage of the TR Q2, the output potential of the circuit 12 can be boosted.

60. 发明专利

JPS63226111A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63226111A
公开(公告)日：1988-09-20
申请号：JP24676387
申请日：1987-09-30
申请人： TOSHIBA CORP
发明人： NAKAI HIROTO , IWAHASHI HIROSHI , ASANO MASAMICHI , KUMAGAI SHIGERU
IPC分类号： H01L21/8238 , G11C11/407 , G11C11/4076 , H01L27/092 , H01L27/10 , H03H11/26 , H03K5/00 , H03K5/1252 , H03K5/13 , H03K5/131 , H03K5/133 , H03K5/134 , H03K5/135
摘要： PURPOSE:To surely obtain a prescribed delay time even when noise enters an input signal by generating an output signal delayed by a prescribed time when the input signal is changed in a prescribed direction and generating an output signal not retarded when the input signal is changed in the opposite direction. CONSTITUTION:The titled circuit consists of a CMOS inverter 1 receiving an input signal B, a transfer gate circuit 2, a charge/discharge capacitor circuit 3, a CMOS inverter 4, a transfer gate circuit 5, a charge/discharge capacitor circuit 6, and an output circuit 7, and an output signal B2 being the result of retarding the input signal B is outputted from the output circuit 7. Then the output signal retarded from the input signal by a prescribed time is generated by charging or discharging the capacitor via a resistor by means of the input signal. Moreover, when the input signal is changed in a direction opposite to the prescribed direction, the output signal not retarded with respect to the input signal is generated. Thus, even if noise is invaded into the signal, a prescribed delay time is surely obtained.

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