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51. 发明专利

JP2003257177A MAGNETIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：JP2003257177A
公开(公告)日：2003-09-12
申请号：JP2002176683
申请日：2002-06-18
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： IWATA YOSHIHISA , AZUMA TOMOTERU
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To propose a read-out method for a cross point type MRAM. SOLUTION: TMR elements MTJ are arranged at intersections of word lines WL1,...WL5 and bit lines BL1,...BL5. one end of each word line WL1,...WL5 is connected to a ground point VSS through row selection switches RSW1,...RSW5. On end of each bit line BL1,...BL5 is connected respectively to bit line bias circuit 13-1,...13-5. At the time of read-out operation, the bit line bias circuit 13-1,...13-5 give a bias potential to all bit lines BL1,...BL5. A selected word line WLi is short-circuited to the ground point VSS, unselected word lines are set in a floating state. COPYRIGHT: (C)2003,JPO

52. 发明专利

JP2003249629A MAGNETIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：JP2003249629A
公开(公告)日：2003-09-05
申请号：JP2002153037
申请日：2002-05-27
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS
发明人： IWATA YOSHIHISA , AZUMA TOMOTERU
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To propose a magnetic random access memory (MRAM) having a cell array structure suitable for high integration of a cell. SOLUTION: A read-out block BK11 is constituted of a plurality of TMR elements 12 arrayed in a lateral direction. One end of the TMR elements 12 in the read-out block BK11 is commonly connected to a source line SL1 via a read-out selection switch RSW. The other ends of the TMR elements 12 are respectively and independently connected to read out bit lines RBL1-RBL 4/write word lines WWL1-WWL4. The read out bit lines RBL1-RBL4/write word lines WWL1-WWL4 are connected to common data lines 30 via a row selection switch RSW2. The common data line 30 is connected to a read-out circuit 29B. COPYRIGHT: (C)2003,JPO

53. 发明专利

JP2003229547A MAGNETIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：JP2003229547A
公开(公告)日：2003-08-15
申请号：JP2002153063
申请日：2002-05-27
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To propose an MRAM of a cell array structure which is suitable for high level integration of cells. SOLUTION: A plurality of blocks from BKj0 to BKjn are connected with read bit lines BLj. The block BKjn has a plurality of MTJ elements 12 which are connected in series with parts between the read bit lines BLj and a ground terminal. The plurality of MTJ elements 12 are, e.g. stacked on a semiconductor substrate. The read bit lines BLj are arranged on the stacked plural MTJ elements. In the vicinity of the plurality of MTJ elements in the block BKjn, write word lines from WWL3n to WWL3n+2 which are stretched in an X direction and write bit lines BLj0, BLj1 which are stretched in a Y direction are arranged. COPYRIGHT: (C)2003,JPO

54. 发明专利

JP2003196978A SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：JP2003196978A
公开(公告)日：2003-07-11
申请号：JP2001391012
申请日：2001-12-25
申请人： TOSHIBA CORP
发明人： FUJITA KATSUYUKI , IWATA YOSHIHISA
IPC分类号： G11C11/407 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which dispersion of read-out current can be suppressed using a memory cell having one transistor structure in which a floating channel body is a storage node. SOLUTION: This device is provided with a memory cell array, a sense amplifier, and a write circuit, the memory cell has a floating channel body, and constituted of MISFET storing a first data state in which the channel body is set to a first potential by a pentode operation and a second data state in which the channel body is set to a second potential by making to flow a forward bias current in a drain junction. The write circuit has a driver 41 outputting respectively high level voltage pentode-operating the memory cell for a drain of a selected memory cell in accordance with a data state to be written and low level voltage required for making to flow a forward bias current in a drain junction, and a current control circuit 42 controlling a write driver 41 so as to be made to flow constant current in a selected memory cell when high level voltage is outputted. COPYRIGHT: (C)2003,JPO

55. 发明专利

JP2002216482A SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2002216482A
公开(公告)日：2002-08-02
申请号：JP2001289888
申请日：2001-09-21
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/14 , G11C11/15 , G11C11/38 , G11C11/419 , G11C13/00 , G11C16/06 , G11C17/18 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which sufficient read-out margin can be obtained by suppressing stress of a current driving type memory cell. SOLUTION: A MTJ-MRAM cell consisting of MTJ and a selection switch transistor QS is used for a memory cell MC. A sense amplifier SA connected to a bit line BL to which data of the memory cell MC are read out is constituted by using an operation amplifier OP. An inverse input terminal of the operation amplifier OP is connected to the bit line BL, and a fixed potential VC is given to a non-inverse input terminal. A drain and a gate of a PMOS transistor Q31 for a clamp used as a current source for charging a bit line are connected to the inverse input terminal of the operation amplifier OP, and a source is feedback-controlled by an output of the operation amplifier OP. Thereby, a clamp potential of the bit line BL is fixed to VC.

56. 发明专利

JP2002190733A CLOCK SYNCHRONIZATION CIRCUIT FOR PHASE COMPENSATION 失效
公开(公告)号：JP2002190733A
公开(公告)日：2002-07-05
申请号：JP2000389062
申请日：2000-12-21
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/4076 , H03K5/00 , H03K5/14 , H03L7/081 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To extend the phase-matchable frequency range of a clock synchronization circuit for phase compensation. SOLUTION: The circuit has a delay line 13 which is obtained by interconnecting plural delay cells 10 having the same configuration in series and to which an external clock Ext.Clk are inputted and a switch circuit 19 capable of switching the dividing number of one period of the external clock by the delay line. The circuit is provided with a core DLL 110a for outputting plural signals expressing plural phases obtained by dividing one period of the external block from the delay cells of respective stages of the delay line, and a peripheral DLL 120 for generating an internal clock Int.Clk obtained by compensating phase shifting from the external clock by selecting hourly continuous biaxial signals from the core DLL and mixing them.

57. 发明专利

JP2002164941A SEMICONDUCTOR DEVICE AND DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JP2002164941A
公开(公告)日：2002-06-07
申请号：JP2000361232
申请日：2000-11-28
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G06F3/00 , G06F13/16 , H01L27/22 , H01L43/06 , H03M1/66 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide a data transmission system with excellent extendability where devices are interconnected in a ring form and data are transmitted in terms of an electric current value. SOLUTION: This invention provides the data transmission system where memory LSIs 2 are interconnected in a ring form and data are transmitted in terms of an electric current value. Each memory LSI 2 is provided with an output terminal LPOUT for outputting a data current, an input terminal LPIN for receiving a data current, an internal current wire 20 that is provided between the input terminal and the output terminal, a transfer switch TG that is inserted on the way of the internal current wire 20, interrupts the internal current wire 20 into an input wire section 20a and an output wire section 20b in the case of data transmission and conducts them at data reception, an output circuit 23 that converts voltage data into a current value and transmits the data current from the output terminal LPOUT and an input circuit 22 that uses a Hall effect element HD to detect the data current received from the input terminal LPIN and to be captured in the internal current wire 20 and converts the data current into a voltage.

58. 发明专利

JP2002057228A SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002057228A
公开(公告)日：2002-02-22
申请号：JP2000242346
申请日：2000-08-10
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/417 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit for preventing characteristics changes due to capacitance coupling between floating gates, and to provide a method for manufacturing the same. SOLUTION: Non-volatile memory transistors, each having the floating gate 5a formed on a silicon substrate 1 via a gate insulating film 4 and a control gate 7a formed on the gate 5a via an inter-gate insulating film 6, are formed integrally. A silicon oxide film 20 is formed in a state isolated from the gate 5a, in between the adjacent memory transistors in the channel longitudinal direction, and the gate 5a is filled in a self-aligned manner between the films 20. Thus, the gate 7a is extended, from the upper surface of the gate 5a to the side face, and the capacity coupling between the adjacent gates 5a is shielded.

59. 发明专利

JP2002056369A NONVOLATILE SEMICONDUCTOR MEMORY CARD 失效
公开(公告)号：JP2002056369A
公开(公告)日：2002-02-20
申请号：JP2001136419
申请日：2001-05-07
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , IWATA YOSHIHISA , ITO YASUO , OHIRA HIDEKO , MASUOKA FUJIO
IPC分类号： B42D15/10 , G06K19/07 , G06K19/077 , G11C16/02 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To perform the data write and data and read using a nonvolatile memory cell at high speed and also sufficiently increase the processing speed even in a larger scale. SOLUTION: This nonvolatile semiconductor memory card using a nonvolatile semiconductor memory comprises an external connecting terminal 35, a plurality of nonvolatile semiconductor memory chips 32 for storing data, one semiconductor memory chip 33 for storing directory information and a control circuit chip 34 for controlling the interface with the outside and each of the chips 32, 33.

60. 发明专利

JP2001273776A CACHE MEMORY SYSTEM, SEMICONDUCTOR MEMORY, NON-VOLATILE SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY VERIFY-CIRCUIT 失效
公开(公告)号：JP2001273776A
公开(公告)日：2001-10-05
申请号：JP2001035052
申请日：2001-02-13
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G06F12/08 , G06F12/00 , G06F12/06 , G06F12/16 , G11C11/41 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten a time required for program-verify and erase-verify and to prevent over-variation of threshold voltage though rewriting and re-erasion are performed. SOLUTION: This cache memory system is provided with a main memory having plural erasing blocks which comprises plural memory cells having the prescribed number of bits and outputting a erasing verify-signal when all of the prescribed number of bits are erased, a cache memory, and a control circuit controlling data transfer operation between the main memory and the cache memory, when accesses data does not exist in the cache memory due to cache- miss-hit, the control circuit erases one data in the plural erasing blocks, after the data is erased completely and the erasing verify-signal is outputted, the control circuit performs data rewriting operation rewriting data of the cache memory in one of the plural erasing blocks.

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