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51. 发明授权

US07285466B2 Methods of forming metal oxide semiconductor (MOS) transistors having three dimensional channels 有权
标题翻译：形成具有三维通道的金属氧化物半导体（MOS）晶体管的方法
公开(公告)号：US07285466B2
公开(公告)日：2007-10-23
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

52. 发明授权

US07285456B2 Method of fabricating a fin field effect transistor having a plurality of protruding channels 有权
标题翻译：制造具有多个突起通道的鳍状场效应晶体管的方法
公开(公告)号：US07285456B2
公开(公告)日：2007-10-23
申请号：US11295770
申请日：2005-12-07
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L21/8238
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.
摘要翻译：在制造具有多个突出通道的鳍状场效应晶体管的方法中，通过在第一硬掩模图案上形成伪栅极图案和在具有有源区域图案的半导体衬底上形成第一绝缘层来形成鳍状场效应晶体管在所述有源区域图案的一部分中形成源极和漏极区域，在所述源极和漏极区域之间形成多个垂直突出的沟道，在所述有源区域图案上形成具有所述多个突出沟道的栅极电介质层，栅极电介质层上的栅电极。

53. 发明申请

US20070111487A1 Highly integrated semiconductor device and method of fabricating the same 有权
标题翻译：高度集成的半导体器件及其制造方法
公开(公告)号：US20070111487A1
公开(公告)日：2007-05-17
申请号：US11600719
申请日：2006-11-17
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L21/20
CPC分类号： H01L27/24
摘要： A method of fabricating a semiconductor device includes sequentially forming a first pattern and a second pattern on a substrate, the second pattern being a non-single-crystalline semiconductor stacked on the first pattern, wherein a portion of the substrate is exposed adjacent to the first and second patterns, forming a non-single-crystalline semiconductor layer on the substrate, the semiconductor layer contacting the second pattern and the exposed portion of the substrate, and, using the substrate as a seed layer, changing the crystalline state of the semiconductor layer to be single-crystalline and changing the crystalline state of the second pattern to be single-crystalline.
摘要翻译：一种制造半导体器件的方法包括在衬底上顺序地形成第一图案和第二图案，第二图案是堆叠在第一图案上的非单晶半导体，其中衬底的一部分暴露在与第一图案相邻的第一图案和第二图案，在衬底上形成非单晶半导体层，与第二图案接触的半导体层和衬底的暴露部分，并且使用衬底作为种子层，改变半导体层的结晶状态为单晶，并将第二图案的结晶状态改变为单晶。

54. 发明授权

US07129541B2 Field effect transistors including vertically oriented gate electrodes extending inside vertically protruding portions of a substrate 有权
标题翻译：场效应晶体管包括在衬底的垂直突出部分内延伸的垂直取向的栅电极
公开(公告)号：US07129541B2
公开(公告)日：2006-10-31
申请号：US10945246
申请日：2004-09-20
申请人： Sung-Min Kim , Hye-Jin Cho , Shin-Ae Lee , Eun-Jung Yun , Dong-Gun Park
发明人： Sung-Min Kim , Hye-Jin Cho , Shin-Ae Lee , Eun-Jung Yun , Dong-Gun Park
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L3/113 , H01L31/119
CPC分类号： H01L29/78696 , H01L29/42336 , H01L29/42384 , H01L29/66787 , H01L29/66825
摘要： A field effect transistor on an active region of a semiconductor substrate includes a vertically protruding thin-body portion of the semiconductor substrate and a vertically oriented gate electrode at least partially inside a cavity defined by opposing sidewalls of the vertically protruding portion of the substrate. The transistor further includes an insulating layer surrounding an upper portion of the vertically oriented gate electrode and a laterally oriented gate electrode on the insulating layer and connected to a top portion of the vertically oriented gate electrode. Accordingly, a T-shaped gate electrode is defined having a lateral portion on a top surface of a semiconductor substrate and having a vertical portion at least partially inside a cavity defined by opposing sidewalls of a vertically protruding portion of the substrate.
摘要翻译：在半导体衬底的有源区域上的场效应晶体管包括半导体衬底的垂直突出的薄体部分和至少部分地在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直取向的栅电极。晶体管还包括围绕垂直取向的栅电极的上部的绝缘层和绝缘层上的横向取向的栅电极，并连接到垂直取向的栅电极的顶部。因此，T形栅电极被限定为具有在半导体衬底的顶表面上的横向部分，并且具有至少部分至少部分在由衬底的垂直突出部分的相对侧壁限定的空腔内的垂直部分。

55. 发明申请

US20060186446A1 3-Dimensional flash memory device and method of fabricating the same 有权
标题翻译： 3维闪存器件及其制造方法
公开(公告)号：US20060186446A1
公开(公告)日：2006-08-24
申请号：US11349287
申请日：2006-02-06
申请人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
发明人： Sung-Min Kim , Eun-Jung Yun , Dong-Won Kim , Jae-Man Yoon
IPC分类号： H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7923 , H01L29/7926
摘要： In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate.
摘要翻译：在一个实施例中，3维快闪存储器件包括：在半导体衬底上沿垂直方向延伸的栅极; 围绕门的电荷存储层; 围绕电荷存储层的硅层; 在所述硅层中垂直形成的沟道区; 以及垂直形成在硅层中的沟道区两侧的源/漏区。可以通过以三维方式存储数据来提高集成度; 可以通过在栅极的两侧提供晶体管来执行2位操作。

56. 发明申请

US20060157753A1 Multi-bit nonvolatile memory devices and methods of manufacturing the same 有权
标题翻译：多位非易失性存储器件及其制造方法
公开(公告)号：US20060157753A1
公开(公告)日：2006-07-20
申请号：US11335390
申请日：2006-01-19
申请人： Sung-Min Kim , Eun-Jung Yun
发明人： Sung-Min Kim , Eun-Jung Yun
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/0692 , H01L29/7923
摘要： Multi-bit nonvolatile memory devices and related methods of manufacturing the same are described. In some multi-bit nonvolatile memory devices, a semiconductor substrate has a recessed region defined therein. An insulating layer, which can include an ONO layer, is configured to store data within programming regions therein, and covers a sidewall and a lower surface of the recess region. A gate electrode is on the insulating layer in the recessed region. At least one pair of impurity regions are in the semiconductor substrate. The impurity regions adjoin a side surface of the insulating layer in the recess region and form a relative angle that is less than 120° therebetween with respect to a center of the gate electrode.
摘要翻译：描述了多位非易失性存储器件及其相关制造方法。在一些多位非易失性存储器件中，半导体衬底具有限定在其中的凹陷区域。可以包括ONO层的绝缘层被配置为在其中的编程区域内存储数据，并且覆盖凹部区域的侧壁和下表面。栅电极位于凹陷区域的绝缘层上。半导体衬底中至少有一对杂质区。杂质区域与凹陷区域中的绝缘层的侧表面相邻，并且相对于栅电极的中心形成小于120°的相对角度。

57. 发明申请

US20050032322A1 Metal oxide semiconductor (MOS) transistors having three dimensional channels and methods of fabricating the same 有权
标题翻译：具有三维通道的金属氧化物半导体（MOS）晶体管及其制造方法
公开(公告)号：US20050032322A1
公开(公告)日：2005-02-10
申请号：US10909471
申请日：2004-08-02
申请人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
发明人： Sung-Min Kim , Dong-Won Kim , Eun-Jung Yun , Dong-Gun Park , Sung-Young Lee , Jeong-Dong Choe , Shin-Ae Lee , Hye-Jin Cho
IPC分类号： H01L29/786 , H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/76 , H01L21/3205
CPC分类号： H01L29/785 , H01L21/26586 , H01L21/823412 , H01L21/823487 , H01L21/823807 , H01L21/823821 , H01L21/823885 , H01L29/66545 , H01L29/66621 , H01L29/66795 , H01L29/7842
摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.
摘要翻译：金属氧化物半导体（MOS）晶体管的单位电池包括在集成电路基板上的集成电路基板和MOS晶体管。 MOS晶体管具有源极区域，漏极区域和栅极区域，栅极区域在源极区域和漏极区域之间。第一和第二沟道区设置在源区和漏区之间。沟道区域由集成电路衬底中的第一和第二间隔开的突起限定，由沟槽区域分隔开。第一和第二突起远离集成电路基板延伸，并且第一和第二突起的上表面与源区和漏区的上表面基本上是平面的。在第一和第二间隔开的突起的侧壁上延伸的沟槽区域中以及在第一和第二间隔开的突起的至少一部分表面上设置栅电极。

58. 发明授权

US06914316B2 Semiconductor trench isolation structure 有权
标题翻译：半导体沟槽隔离结构
公开(公告)号：US06914316B2
公开(公告)日：2005-07-05
申请号：US10617742
申请日：2003-07-14
申请人： Eun-Jung Yun , Sung-Eui Kim
发明人： Eun-Jung Yun , Sung-Eui Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L21/76229
摘要： A trench structure of a semiconductor device includes first and second regions of a substrate having first and second trenches, respectively, the first trench having an aspect ratio larger than that of the second trench, a first insulation material on a bottom and sidewalls of the first trench forming a first sub-trench in the first trench, a second insulation material completely filling the first sub-trench, a third insulation material formed on a bottom and sidewalls of the second trench forming a second sub-trench in the second trench, a fourth insulation material formed on a bottom and sidewalls of the second sub-trench, and a fifth insulation material completely filling a third sub-trench formed in the second sub-trench by the fourth insulation material.
摘要翻译：半导体器件的沟槽结构包括分别具有第一和第二沟槽的衬底的第一和第二区域，第一沟槽的纵横比分别大于第二沟槽的纵横比，第一绝缘材料位于第一和第二沟槽的底部和侧壁上在所述第一沟槽中形成第一子沟槽的沟槽，完全填充所述第一子沟槽的第二绝缘材料，形成在所述第二沟槽的底部和侧壁上的第三绝缘材料，所述第二沟槽在所述第二沟槽中形成第二子沟槽，第四绝缘材料形成在第二子沟槽的底部和侧壁上，第五绝缘材料通过第四绝缘材料完全填充形成在第二子沟槽中的第三子沟槽。

59. 发明授权

US07791936B2 Multibit electro-mechanical memory device and method of manufacturing the same 有权
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US07791936B2
公开(公告)日：2010-09-07
申请号：US12074645
申请日：2008-03-05
申请人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
发明人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
IPC分类号： G11C11/50
CPC分类号： H01L27/10 , G11C11/50 , H01H59/0009 , H01L27/105 , H01L27/115 , Y10T29/49105
摘要： A multibit electro-mechanical memory device and a method of manufacturing the same include a substrate, a bit line on the substrate; a lower word line and a trap site isolated from the bit line, a pad electrode isolated from a sidewall of the trap site and the lower word line and connected to the bit line, a cantilever electrode suspended over a lower void in an upper part of the trap site, and connected to the pad electrode and curved by an electrical field induced by a charge applied to the lower word line, a contact part for concentrating a charge induced from the cantilever electrode thereon in response to the charge applied from the lower word line and the trap site, the contact part protruding from an end part of the cantilever electrode, and an upper word line formed with an upper void above the cantilever electrode.
摘要翻译：多位机电存储器件及其制造方法包括衬底，衬底上的位线; 与位线隔离的下部字线和陷阱位置，从陷阱位置的侧壁和下部字线隔离并连接到位线的焊盘电极，悬挂在上部的下部空隙上的悬臂电极陷阱位置，并且连接到焊盘电极并由施加到下字线的电荷引起的电场弯曲;接触部分，用于响应于从下位词施加的电荷而将从悬臂电极引起的电荷聚集在其上线和捕获部位，从悬臂电极的端部突出的接触部分和在悬臂电极上方形成有上部空隙的上字线。

60. 发明申请

US20090072297A1 Multibit electro-mechanical memory device and method of manufacturing the same 审中-公开
标题翻译：多位机电记忆体装置及其制造方法
公开(公告)号：US20090072297A1
公开(公告)日：2009-03-19
申请号：US12154474
申请日：2008-05-23
申请人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
发明人： Ji-Myoung Lee , Min-Sang Kim , Eun-Jung Yun , Sung-Young Lee , In-Hyuk Choi
IPC分类号： H01L21/28 , H01L29/792
CPC分类号： H01L27/10 , B82Y10/00 , G11C11/56 , G11C13/025 , G11C23/00
摘要： A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second portion of the cantilever electrode and the lower word line, and wherein the second portion of the cantilever electrode, in a first position, is curved, wherein a trap site extends above the cantilever electrode, the trap site separated from the cantilever electrode by an upper void, and wherein an upper word line on the trap site receives a charge that enables the second portion of the cantilever electrode, in a second position, to be curved toward the trap site.
摘要翻译：存储器件包括悬臂电极，其包括由焊盘电极支撑的第一部分，并且从焊盘电极延伸的第一部分，还包括在下部字线的上部上拱起的第二部分，其中下部空隙为在所述悬臂电极的第二部分和所述下字线之间，并且其中所述悬臂电极的第二部分处于第一位置是弯曲的，其中捕获位置在所述悬臂电极上方延伸，所述捕获部位与所述悬臂电极分离通过上部空隙，并且其中陷阱位置处的上部字线接收电荷，使得悬臂电极的第二部分在第二位置能够朝向陷阱位置弯曲。

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