专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US5457417A Scaler circuit 失效
标题翻译：整流电路
公开(公告)号：US5457417A
公开(公告)日：1995-10-10
申请号：US191495
申请日：1994-02-04
申请人： Shou Guoliang , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Shou Guoliang , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/14 , G06G7/12 , G06J1/00 , H03F3/34 , H03G1/00 , H03G3/00 , H03G3/10 , G06F7/44
CPC分类号： G06G7/12 , G06J1/00 , H03G1/0094
摘要： A scalar circuit includes serially connected inverters connected to one another via a plurality of connecting lines. A plurality of input lines are provided to the input of a first inverter in the serially connected inverters. A plurality of feedback lines are provided between the input and output of each inverter. A capacitance and a switch is provided in each connecting line, input line and feedback line. The switch connects a terminal of the capacitance to ground while simultaneously disconnecting the ends of that line from one another. The switches are cooperatively actuated so that the effective composite capacitance in the feedback lines and the connecting lines are substantially equal. In addition, the composite capacitance of in the input lines and the connecting lines are substantially equal.
摘要翻译：标量电路包括通过多条连接线彼此连接的串联逆变器。多个输入线被提供给串联逆变器中的第一反相器的输入端。在每个逆变器的输入和输出之间提供多条反馈线。每个连接线，输入线和反馈线都提供电容和开关。开关将电容的端子连接到地，同时断开该线的端部。这些开关被协同地致动，使得反馈线和连接线中的有效复合电容基本相等。此外，输入线和连接线中的复合电容基本相等。

52. 发明授权

US5452336A Memory device for recording a time factor 失效
标题翻译：用于记录时间因素的记忆装置
公开(公告)号：US5452336A
公开(公告)日：1995-09-19
申请号：US151030
申请日：1993-11-12
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G04G99/00 , G11C27/00 , H03M1/56 , H03M1/58 , H03K21/02 , H03K17/30
CPC分类号： H03M1/58 , H03M1/56
摘要： A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.
摘要翻译：用于记录数据的时间因子的存储器件包括阈值元件，耦合电容，RC电路和数字计数器。参考电压被输入到RC电路。 RC电路的输出和输入电压各自输入到耦合电容。耦合电容的输出被输入到阈值元件。当由阈值元件接收的电压达到阈值电压电平时，阈值元件产生输出电压。数字计数器接收阈值元件输出电压和参考电压。数字计数器由参考电压触发，开始计数由参考时钟产生的时钟脉冲。数字计数器然后由阈值元件输出电压触发，以停止对时钟脉冲的计数。

53. 发明授权

US5434529A Signal integration circuit 失效
标题翻译：信号积分电路
公开(公告)号：US5434529A
公开(公告)日：1995-07-18
申请号：US142939
申请日：1993-10-29
申请人： Gouliang Shou , Sunao Takatori , Makoto Yamamoto
发明人： Gouliang Shou , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/12 , G06G7/14 , G06G7/60 , H03K5/08 , H03K7/08 , H03K17/687
CPC分类号： H03K7/08
摘要： A signal integration circuit having a first MOSFET including a drain connected to a power source and a gate connected to a plural number of the first capacitances in parallel; and an input means connected to each capacitance; in which each input means comprises; the second MOSFET whose source is connected to the first capacitance through a resistance, which receives an input pulse signal, and whose gate is grounded through the second capacitance, and the third MOSFET whose source is connected to a gate of the second MOSFET, whose drain is connected to a power source, and whose gate receives a pulse signal for setting weight; a gate of the first MOSFET receiving a reference saw-tooth signal, a source of the first MOSFET grounded through the third capacitance, and an output pulse signal being output from this source of said first MOSFET.
摘要翻译：一种信号积分电路，具有包括连接到电源的漏极和与多个第一电容并联连接的栅极的第一MOSFET; 以及连接到每个电容的输入装置; 每个输入装置包括：所述第二MOSFET的源极通过电阻连接到所述第一电容，所述电阻接收输入脉冲信号，并且其栅极通过所述第二电容接地，所述第三MOSFET的源极连接到所述第二MOSFET的栅极，连接到电源，其门接收用于设定权重的脉冲信号; 第一MOSFET的栅极接收参考锯齿信号，通过第三电容接地的第一MOSFET的源极和从该第一MOSFET的源极输出的输出脉冲信号。

54. 发明授权

US5424965A Multiplication circuit for multiplying analog values 失效
标题翻译：用于乘法运算的乘法电路
公开(公告)号：US5424965A
公开(公告)日：1995-06-13
申请号：US172393
申请日：1993-12-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/16 , G06J1/00
CPC分类号： G06J1/00
摘要： A multiplication circuit for multiplying analog values. The multiplication circuit receives a plurality of input voltages and selects one of the input voltages. The multiplication circuit also includes at least one resistor/capacitor (RC) circuit. The RC circuits includes a resistor for receiving a stepwise start signal and a capacitor, which is connected between a ground potential and the resistor. An output terminal is connected between the resistor and the capacitor. The output terminal outputs an output voltage. The multiplication circuit produces a stop signal when a difference between the selected one of the input voltages and the output voltage is greater than a predetermined value. The multiplication circuit selectively increases or decreases a count value by a number of clock pulses that occur between the stepwise start signal and the stop signal, The multiplication circuit produces a count signal, which is indicative of the count value. The multiplication circuit includes a switch for electrically disconnecting, in accordance with the count signal, the resistor and the capacitor of the RC circuit.
摘要翻译：用于乘以模拟值的乘法电路。乘法电路接收多个输入电压并选择输入电压之一。乘法电路还包括至少一个电阻器/电容器（RC）电路。 RC电路包括用于接收逐步启动信号的电阻器和连接在接地电位和电阻器之间的电容器。输出端连接在电阻和电容之间。输出端输出输出电压。当选择的输入电压和输出电压之间的差异大于预定值时，乘法电路产生停止信号。乘法电路选择性地将计数值增加或减少在逐步启动信号和停止信号之间发生的时钟脉冲数。乘法电路产生计数信号，其表示计数值。乘法电路包括根据计数信号电路断开RC电路的电阻器和电容器的开关。

55. 发明授权

US5416850A Associative pattern conversion system and adaption method thereof 失效
标题翻译：关联模式转换系统及其适应方法
公开(公告)号：US5416850A
公开(公告)日：1995-05-16
申请号：US33465
申请日：1993-03-18
申请人： Sunao Takatori , Ryohei Kumagai , Makoto Yamamoto
发明人： Sunao Takatori , Ryohei Kumagai , Makoto Yamamoto
IPC分类号： G06K9/66 , G06N3/063 , G06K9/62
CPC分类号： G06K9/66 , G06N3/063
摘要： An associative pattern conversion system is disclosed which may be used for image recognition. The system includes an image input portion, an image processing portion and a recognition portion. The image processing portion includes a process unit for extracting characteristics and a frame memory for holding image data. The recognition portion, which includes a component for the learning of data to be associated, obtains the extracted characteristics from the image processing portion and performs associative pattern conversion from the image input portion. The system of the present invention may be applied to any neural network, preferably a matrix calculation type neural network.
摘要翻译：公开了可用于图像识别的关联图案转换系统。该系统包括图像输入部分，图像处理部分和识别部分。图像处理部分包括用于提取特征的处理单元和用于保存图像数据的帧存储器。包括用于学习要关联的数据的组件的识别部分从图像处理部分获得提取的特征，并且从图像输入部分执行关联模式转换。本发明的系统可以应用于任何神经网络，优选矩阵计算型神经网络。

56. 发明授权

US5396446A Digital filter circuit that minimizes holding errors transmitted between holding circuits 失效
标题翻译：数字滤波电路使保持电路之间传输的保持误差最小化
公开(公告)号：US5396446A
公开(公告)日：1995-03-07
申请号：US155809
申请日：1993-11-23
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06J1/00 , H03H17/02 , G06G7/02
CPC分类号： H03H17/0294 , G06J1/00 , H03H17/0225
摘要： A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.
摘要翻译：控制保持误差使得将这些误差保持在最小的滤波器电路。在滤波器电路中，乘法电路的乘法器存储在移位寄存器中，并且通过在移位寄存器中循环乘法器，在乘法电路中通过各种乘法器连续执行乘法运算。

57. 发明授权

US5381352A Circuit for multiplying an analog value by a digital value 失效
标题翻译：将模拟值乘以数字值的电路
公开(公告)号：US5381352A
公开(公告)日：1995-01-10
申请号：US170731
申请日：1993-12-21
申请人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
发明人： Guoliang Shou , Weikang Yang , Sunao Takatori , Makoto Yamamoto
IPC分类号： G06G7/16 , G06J1/00 , H03M1/80
CPC分类号： G06J1/00 , H03M1/804
摘要： A multiplication circuit directly multiplying an analog and a digital data without converting analog/digital or digital/analog converting. An analog input voltage is controlled by a switching signal of a digital voltage so as to generate an analog output or cut-off the outputs. Digital input signals b.sub.0 to b.sub.7 of a plural number of bits is integrated giving weights by means of a capacitive coupling, and a sign bit is added by a capacitive coupling CP with a double weight of the most significant bit ("MSB") of the digital input.
摘要翻译：乘法电路将模拟和数字数据直接相乘，而无需转换模拟/数字或数字/模拟转换。模拟输入电压由数字电压的开关信号控制，以产生模拟输出或截止输出。多个位的数字输入信号b0至b7被积分，通过电容耦合给出加权，并且通过电容耦合CP加上符号位，该电容耦合CP具有最高有效位（“MSB”）的双重权重数字输入

58. 发明授权

US06169771A Matched filter for spread spectrum communication systems and hybrid analog-digital transversal filter 失效
标题翻译：用于扩频通信系统和混合模数转换滤波器的匹配滤波器
公开(公告)号：US06169771A
公开(公告)日：2001-01-02
申请号：US09014264
申请日：1998-01-27
申请人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Xuping Zhou , Xiaoling Oin , Kazunori Motohashi , Makoto Yamamoto , Sunao Takatori
IPC分类号： H04L2706
CPC分类号： H03H17/0254 , H04B1/7093
摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.
摘要翻译：一方面，本发明提供一种低功耗匹配滤波器。在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。通过移位寄存器中的系数来防止采样数据传输错误存储。采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。加法电路以相同的方式刷新。

59. 发明授权

US06031415A Matched filter circuit for spread spectrum communication 失效
标题翻译：用于扩频通信的匹配滤波电路
公开(公告)号：US06031415A
公开(公告)日：2000-02-29
申请号：US733820
申请日：1996-10-18
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Mamoru Sawahashi , Fumiyuki Adachi , Sunao Takatori
IPC分类号： H04J13/00 , H03H17/02 , H04B1/7093 , H03K5/00 , H03D1/00
CPC分类号： H03H17/0254 , H04B1/707
摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.
摘要翻译：本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

60. 发明授权

US5926512A Matched filter circuit 失效
标题翻译：匹配滤波电路
公开(公告)号：US5926512A
公开(公告)日：1999-07-20
申请号：US735787
申请日：1996-10-23
申请人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
发明人： Guoliang Shou , Changming Zhou , Makoto Yamamoto , Sunao Takatori , Mamoru Sawahashi , Fumiyuki Adachi
IPC分类号： H04J13/00 , H03H11/04 , H03H17/02 , H03H19/00 , H04B1/7093 , H03D1/00 , H04L27/06
CPC分类号： H03H11/04 , H03H17/0254 , Y02B60/50
摘要： A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.
摘要翻译：公开了一种用于移动通信的匹配滤波器电路。该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此，抽样操作。每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式