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51. 发明授权

US08415669B2 Semiconductor display device 有权
标题翻译：半导体显示装置
公开(公告)号：US08415669B2
公开(公告)日：2013-04-09
申请号：US13217322
申请日：2011-08-25
申请人： Shunpei Yamazaki , Satoshi Murakami , Masahiko Hayakawa , Kiyoshi Kato , Mitsuaki Osame
发明人： Shunpei Yamazaki , Satoshi Murakami , Masahiko Hayakawa , Kiyoshi Kato , Mitsuaki Osame
IPC分类号： H01L29/786
CPC分类号： H01L27/1248 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L27/1244 , H01L27/1255 , H01L27/13 , H01L27/3246 , H01L27/3276 , H01L33/52 , H01L51/5237 , H01L51/5253
摘要： It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulating film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.
摘要翻译：本发明的目的是提供一种具有层间绝缘膜的半导体显示装置，其可以在控制成膜时间的同时获得表面的平面性，并且可以控制用于除去水分的加热处理的处理时间，并且可以防止水分在层间绝缘膜中不被放电到与层间绝缘膜相邻的膜或电极。形成与有机树脂相比不容易透过水分的含氮的无机绝缘膜，以覆盖TFT。接着，在有机绝缘膜上涂布含有感光性丙烯酸树脂的有机树脂膜，将有机树脂膜部分地曝光以打开。此后，形成与有机树脂相比不容易透过水分的含有氮的无机绝缘膜，以覆盖打开的有机树脂膜。然后，在有机树脂膜的开口部分中，通过蚀刻部分地打开栅极绝缘膜和含氮的两层无机绝缘膜，以暴露TFT的有源层。

52. 发明申请

US20120161127A1 MEMORY DEVICE, MEMORY MODULE AND ELECTRONIC DEVICE 有权
标题翻译：存储器件，存储器模块和电子器件
公开(公告)号：US20120161127A1
公开(公告)日：2012-06-28
申请号：US13331645
申请日：2011-12-20
申请人： Kiyoshi Kato , Jun Koyama , Toshihiko Saito , Shunpei Yamazaki
发明人： Kiyoshi Kato , Jun Koyama , Toshihiko Saito , Shunpei Yamazaki
IPC分类号： H01L29/78
CPC分类号： H01L27/1156 , G11C11/404 , H01L27/1225
摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.
摘要翻译：第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜并且在第二通道形成区域和第三栅电极之间。第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

53. 发明申请

US20120012837A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120012837A1
公开(公告)日：2012-01-19
申请号：US13175542
申请日：2011-07-01
申请人： Shunpei Yamazaki , Kiyoshi Kato , Shuhei Nagatsuka
发明人： Shunpei Yamazaki , Kiyoshi Kato , Shuhei Nagatsuka
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , G11C16/0433 , G11C16/26 , H01L27/11517 , H01L27/1156 , H01L27/1211 , H01L27/1225
摘要： A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(εra/εrb)
摘要翻译：具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。第一晶体管和第二晶体管被设置为至少部分地彼此重叠。第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（＆egr; rb /＆egr; ra）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示厚度绝缘层的介电常数表示绝缘层的介电常数，rb表示绝缘层的介电常数。

54. 发明申请

US20110147737A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110147737A1
公开(公告)日：2011-06-23
申请号：US12966611
申请日：2010-12-13
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L29/12
CPC分类号： H01L27/115 , G11C16/0416 , H01L21/28518 , H01L23/528 , H01L27/10805 , H01L27/10855 , H01L27/11517 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L27/1255 , H01L28/40 , H01L29/24 , H01L29/6659 , H01L29/78 , H01L29/7869 , H01L2924/0002 , H01L2924/00
摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.
摘要翻译：第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 并且设置包括第二源电极和第二漏电极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏极之一重叠的电极。第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

55. 发明申请

US20110128777A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110128777A1
公开(公告)日：2011-06-02
申请号：US12952609
申请日：2010-11-23
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： G11C11/24 , H01L29/12 , G11C7/00
CPC分类号： G11C11/405 , G11C16/0425 , H01L21/8221 , H01L27/0688 , H01L27/105 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225
摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
摘要翻译：半导体器件包括第一布线; 第二布线第三线; 第四布线具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。第一晶体管形成在包括半导体材料的衬底上或衬底中。第二晶体管包括氧化物半导体层。

56. 发明申请

US20110121286A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110121286A1
公开(公告)日：2011-05-26
申请号：US12949641
申请日：2010-11-18
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： H01L27/092
CPC分类号： H01L21/02554 , G11C11/403 , G11C11/405 , G11C16/0425 , H01L21/02565 , H01L21/02631 , H01L21/02664 , H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225
摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.
摘要翻译：本发明的目的是提供一种具有新颖结构的半导体器件。半导体器件包括彼此串联连接的存储单元和电容器。一个存储单元包括连接到位线和源极线的第一晶体管，连接到信号线和字线的第二晶体管，以及连接到字线的电容器。第二晶体管包括氧化物半导体层。第一晶体管的栅电极，第二晶体管的源电极和漏电极之一以及电容器的一个电极彼此连接。

57. 发明申请

US20110116310A1 SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF 有权
标题翻译：半导体器件及其驱动方法
公开(公告)号：US20110116310A1
公开(公告)日：2011-05-19
申请号：US12945476
申请日：2010-11-12
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： G11C11/4096
CPC分类号： G11C7/062 , G11C7/067 , G11C11/40 , G11C2207/005 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/0688 , H01L27/105 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11551 , H01L27/1156 , H01L27/1203 , H01L27/1225 , H01L29/155 , H01L29/205
摘要： A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.
摘要翻译：半导体器件包括：源极线; 有点线字线连接到位线和字线的存储单元; 驱动电路，其驱动多个第二信号线和多个字线，以选择由地址信号指定的存储单元; 产生写入电位和多个读取电位以供应到写入电路和读取电路的电位产生电路; 以及控制电路，其基于将所述位线的电位与所述多个读取电位进行比较的所述读取电路的结果来选择用于校正的多个电压中的一个。

58. 发明申请

US20090289341A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090289341A1
公开(公告)日：2009-11-26
申请号：US12468284
申请日：2009-05-19
申请人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
发明人： Shunpei Yamazaki , Yoshiaki Oikawa , Hironobu Shoji , Yutaka Shionoiri , Kiyoshi Kato , Masataka Nakada
IPC分类号： H01L23/02
CPC分类号： G06K19/07749 , G06K19/07735 , H01L27/1214 , H01L27/1218 , H01L27/1266 , H01L27/13 , H01Q1/38 , H01Q7/00
摘要： An object is to provide a highly reliable semiconductor device having resistance to external stress and electrostatic discharge while achieving reduction in thickness and size. Another object is to prevent defective shapes and deterioration in characteristics due to external stress or electrostatic discharge in a manufacture process to manufacture a semiconductor device with a high yield. A first insulator and a second insulator facing each other, a semiconductor integrated circuit and an antenna provided between the first insulator and the second insulator facing each other, a conductive shield provided on one surface of the first insulator, and a conductive shield provided on one surface of the second insulator are provided. The conductive shield provided on one surface of the first insulator and the conductive shield provided on one surface of the second insulator are electrically connected.
摘要翻译：目的是提供一种具有耐外部应力和静电放电的高度可靠的半导体器件，同时实现厚度和尺寸的减小。另一个目的是在制造过程中防止由于外部应力或静电放电而导致的形状不良和特性劣化，从而以高产率制造半导体器件。第一绝缘体和第二绝缘体彼此面对，半导体集成电路和设置在第一绝缘体和第二绝缘体之间彼此面对的天线，设置在第一绝缘体的一个表面上的导电屏蔽和设置在第一绝缘体上的导电屏蔽提供第二绝缘体的表面。设置在第一绝缘体的一个表面上的导电屏蔽和设置在第二绝缘体的一个表面上的导电屏蔽电连接。

59. 发明授权

US07596024B2 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US07596024B2
公开(公告)日：2009-09-29
申请号：US11776973
申请日：2007-07-12
申请人： Kiyoshi Kato , Shunpei Yamazaki
发明人： Kiyoshi Kato , Shunpei Yamazaki
IPC分类号： G11C16/04
CPC分类号： G11C8/10 , G11C8/12 , G11C8/14 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/12 , H01L27/124
摘要： A highly-integrated nonvolatile memory. A memory cell array where plural memory cells are arranged in matrix in row and column directions, plural first and second word lines, and plural bit lines are included. Each of the plural memory cells includes a first memory transistor and a second memory transistor which are connected in series. A gate electrode of the first memory transistor is connected to the first word line, a gate electrode of the second memory transistor is connected to the second word line, one of source and drain regions of the first memory transistor is connected to the first bit line, and one of source and drain regions of the second memory transistor is connected to the second bit line. Each of the first bit line and the second bit line is provided in common for memory cells in columns which are adjacent to each other.
摘要翻译：高度集成的非易失性存储器。存储单元阵列，其中多个存储单元以行和列方向排列成矩阵，多个第一和第二字线以及多个位线。多个存储单元中的每一个包括串联连接的第一存储晶体管和第二存储晶体管。第一存储晶体管的栅电极连接到第一字线，第二存储晶体管的栅电极连接到第二字线，第一存储晶体管的源极和漏极区之一连接到第一位线并且第二存储晶体管的源极和漏极区中的一个连接到第二位线。第一位线和第二位线中的每一个被共同地设置在彼此相邻的列中的存储器单元。

60. 发明授权

US06914818B2 Non-volatile memory and semiconductor device 有权
标题翻译：非易失性存储器和半导体器件
公开(公告)号：US06914818B2
公开(公告)日：2005-07-05
申请号：US10383209
申请日：2003-03-06
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , G11C16/26 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/0433 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32
摘要： There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.
摘要翻译：提供了一种在写入操作中实现高精度阈值控制的非易失性存储器。在本发明中，控制存储晶体管的漏极电压和漏极电流，进行热电子注入系统的写入动作，其中电荷注入速度不依赖于阈值电压。图图1A和1B是用于控制写入的电路结构的视图。在图如图1A和1B所示，运算放大器103的输出端连接到存储晶体管101的控制栅极，恒流源102连接到漏电极，源电极接地。恒流源102和电压Vpgm分别连接到运算放大器103的两个输入端。

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