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51. 发明授权

US5247521A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5247521A
公开(公告)日：1993-09-21
申请号：US848547
申请日：1992-03-09
申请人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
发明人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
IPC分类号： G06F11/267 , G06F15/78
CPC分类号： G06F11/2236 , G06F15/7814
摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.
摘要翻译：在单片机中，形成诸如中央处理单元（CPU），用于存储程序的ROM，用于存储数据的RAM和用于输入和数据输出的I / O电路等功能块在一个半导体衬底上。地址数据用于选择CPU必须提供地址数据的内部总线中的功能块的预定区域。缓冲电路能够从外部设备提供地址数据，并且被提供在微计算机中。当功能块被测试时，地址数据直接从外部测试器提供给功能块，而不用CPU的指令执行，并且必要的数据从预定功能块的区域输出，通过缓冲电路，并且是直接读取外部设备。因此，提高了测试效率。

52. 发明授权

US5142536A Data processor 失效
标题翻译：数据处理器
公开(公告)号：US5142536A
公开(公告)日：1992-08-25
申请号：US584608
申请日：1990-09-19
申请人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
发明人： Yasushi Akao , Shinkichi Hotta , Haruo Keida
IPC分类号： G06F11/22 , G06F11/267 , G06F15/78
CPC分类号： G06F11/2236 , G06F15/7814
摘要： In a single chip microcomputer, functional blocks such as the central processing unit (CPU), the ROM for storing programs, the RAM for storing the data and the I/O circuit for the input and the output of the data and the like are formed on one semiconductor substrate. Address data is used for selecting predetermined areas of the functional blocks in the internal bus to which the address data must be supplied by the CPU. A buffer circuit is capable of being supplied with address data from the external devices and is provided in the microcomputer. When the functional blocks are tested, address data is directly supplied to the functional blocks from the external tester without using the instruction execution of the CPU, and necessary data is outputted from the area of the predetermined functional block, passing through the buffer circuit and is read out directly to the external devices. Hence, the testing efficiency is improved.

53. 发明授权

US5005121A Integrated CPU and DMA with shared executing unit 失效
标题翻译：具有共享执行单元的集成CPU和DMA
公开(公告)号：US5005121A
公开(公告)日：1991-04-02
申请号：US326472
申请日：1989-03-20
申请人： Kunihiko Nakada , Yasushi Akao
发明人： Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F9/26 , G06F9/22 , G06F13/10 , G06F13/28 , G06F15/78
CPC分类号： G06F13/285
摘要： A data processor controller for a microprogramming system is constructed with a single operation execution unit serving both a microprocessor and a peripheral device such as a direct memory access controller. In addition to the single operation execution unit, the controller includes a micro-memory which stores micro-instructions for controlling both the microprocessor and the peripheral device, and address registers, multiplexers and decoders integrated into a single device. Different ROM address registers in the controller are separately assigned to provide an address decoder with addresses of selected memory locations in the micro-memory containing the micro-instructions for the microprocessor and the peripheral device, thereby enabling the controller, through multiplexing between the address registers, to use the arithmetic execution unit, counter and bus interface of the single operation exeuction unit on a time sharing basis, for controlling the functions of both the microprocessor and the peripheral device.
摘要翻译：用于微程序系统的数据处理器控制器由单个操作执行单元构成，该单个操作执行单元用于微处理器和诸如直接存储器访问控制器的外围设备。除了单个操作执行单元之外，控制器还包括微存储器，其存储用于控制微处理器和外围设备的微指令，以及集成到单个设备中的地址寄存器，复用器和解码器。控制器中的不同的ROM地址寄存器被分别分配给地址解码器，该地址解码器具有包含微处理器和外围设备的微指令的微存储器中所选择的存储器位置的地址，从而使控制器能够通过地址寄存器在时间分配的基础上使用单个操作单元的算术执行单元，计数器和总线接口，用于控制微处理器和外围设备的功能。

54. 发明授权

US07054990B1 External storage device using non-volatile semiconductor memory 有权
标题翻译：使用非易失性半导体存储器的外部存储设备
公开(公告)号：US07054990B1
公开(公告)日：2006-05-30
申请号：US09635217
申请日：2000-08-10
申请人： Takayuki Tamura , Jun Kitahara , Toru Owada , Shinichi Sawamura , Takeshi Asahi , Nagamasa Mizushima , Takashi Totsuka , Yasushi Akao
发明人： Takayuki Tamura , Jun Kitahara , Toru Owada , Shinichi Sawamura , Takeshi Asahi , Nagamasa Mizushima , Takashi Totsuka , Yasushi Akao
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F12/1466 , G11C7/24 , G11C16/22
摘要： The external storage device according to the present invention which uses a non-volatile semiconductor memory such as a flash memory is provided with plural areas which store user data, and restricts access to the user data from a host computer and also dynamically changes an area an access to which is to be restricted. Accordingly, the ease of use of the external storage device for the host computer is improved. Specifically, the interior of the flash memory is divided into a normal area not protected by a password or the like and a protected area protected by a password or the like. A microprocessor controls accesses to the normal area and the protected area in accordance with a command from the host computer. In addition, the host computer can access the protected area after passing through authentication using a password. Moreover, the host computer changes information indicative of the location of the protected area, thereby dynamically changing the protection area.
摘要翻译：根据本发明的使用诸如闪速存储器的非易失性半导体存储器的外部存储装置设置有存储用户数据的多个区域，并且限制从主计算机访问用户数据，并且还动态地改变区域访问被限制。因此，提高了用于主计算机的外部存储装置的易用性。具体地说，闪速存储器的内部被划分为不受密码等保护的正常区域和由密码等保护的保护区域。微处理器根据主计算机的命令控制对正常区域和保护区域的访问。此外，主机通过使用密码的认证后，可以访问保护区域。此外，主计算机改变指示保护区域的位置的信息，从而动态地改变保护区域。

55. 发明授权

US06668266B2 Data processing device having a central processing unit and digital signal processing unit 失效
标题翻译：具有中央处理单元和数字信号处理单元的数据处理装置
公开(公告)号：US06668266B2
公开(公告)日：2003-12-23
申请号：US09973734
申请日：2001-10-11
申请人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
发明人： Atsushi Kiuchi , Yuji Hatano , Toru Baji , Koki Noguchi , Yasushi Akao , Shiro Baba
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30043
摘要： In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.
摘要翻译：在其中用于控制整个系统的中央处理单元和具有有效处理数字信号所需的乘积和功能的数字信号处理单元的微型计算机和数字信号处理单元安装在同一芯片上，处理次数的增加防止由计算器处理的不同类型的数据引起的步骤，从而提高数字信号处理的效率。

56. 发明授权

US5900008A Semiconductor integrated circuit device 失效
公开(公告)号：US5900008A
公开(公告)日：1999-05-04
申请号：US769188
申请日：1996-12-18
申请人： Yasushi Akao , Kenichi Kuroda
发明人： Yasushi Akao , Kenichi Kuroda
IPC分类号： G06F12/06 , G06F15/78 , G06F13/00
CPC分类号： G06F15/7814
摘要： A semiconductor integrated circuit device comprising a one-chip microcomputer having a nonvolatile memory circuit to and from which write and read operations are carried out at high speed in keeping with the cycle time of the processor. Part of the memory circuit is set aside as a read-only area for accommodating a data processing program, and the rest of the memory is used to write and read data thereto and therefrom. With no need to optimize the assignments of the ROM and RAM parts in the memory circuit, the one-chip microchip is easy to design and manufacture with high productivity. With the program storage area established as desired, users enjoy more convenience use of the one-chip microcomputer than before.

57. 发明授权

US5410658A Microprocessor for carrying out a plurality of different microprograms at the same time and method for controlling the microprocessor 失效
标题翻译：用于同时执行多个不同微程序的微处理器以及用于控制微处理器的方法
公开(公告)号：US5410658A
公开(公告)日：1995-04-25
申请号：US960505
申请日：1992-10-13
申请人： Terumi Sawase , Yasushi Akao
发明人： Terumi Sawase , Yasushi Akao
IPC分类号： G06F9/26 , G06F9/28 , G06F9/38 , G06T9/06
CPC分类号： G06F9/28 , G06F9/3851
摘要： The inventive microprocessor includes a first section which runs a microprogram pertinent to a macroinstruction and a second section which runs microprograms that are independent of the macroinstruction, with the first and second sections being operated selectively under time-division control. The microprocessor operates by either selecting one of a plurality of microaddress registers or a macroinstruction register, and by reading out the contents of the selected register for use as an address of a microinstruction memory, carrying out a process based on a microinstruction read out of the microinstruction memory in accordance with the address and generating a next macroinstruction address or next microinstruction address, making access to a macroinstruction memory in accordance with the next macroinstruction address thereby to read out a next macroinstruction, loading the next macroinstruction into the macroinstruction register, selecting one of the microaddress registers and loading the next microinstruction address into the selected microinstruction register, and controlling the selecting operations on a time-division basis.
摘要翻译：本发明的微处理器包括运行与宏指令相关的微程序的第一部分和运行独立于宏指令的微程序的第二部分，其中第一和第二部分选择性地在时分控制下操作。微处理器通过选择多个微地址寄存器或宏指令寄存器之一进行操作，并且通过读出所选择的寄存器的内容以用作微指令存储器的地址，执行基于从该指令读出的微指令的处理微指令存储器根据地址生成下一个宏指令地址或下一个微指令地址，根据下一个宏指令地址访问宏指令存储器，从而读出下一个宏指令，将下一个宏指令加载到宏指令寄存器中，选择一个的微地址寄存器，并将下一个微指令地址加载到所选择的微指令寄存器中，并且以时分方式控制选择操作。

58. 发明授权

US5226173A Integrated data processor having mode control register for controlling operation mode of serial communication unit 失效
标题翻译：具有用于控制串行通信单元的操作模式的模式控制寄存器的集成数据处理器
公开(公告)号：US5226173A
公开(公告)日：1993-07-06
申请号：US850856
申请日：1992-03-13
申请人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
发明人： Hisao Sasaki , Takeshi Miyazaki , Shiro Baba , Kunihiko Nakada , Yasushi Akao
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.
摘要翻译：用于将从串行输入电路提供的数据提供给内部总线的接收单元和用于将从内部总线提供的数据提供给串行输出电路的传输单元保持从HDLC程序，BI-SYNC中选择的至少两种类型的控制程序作为用于数据发送/接收的控制过程的程序和起始 - 停止同步过程，并且可以基于由处理器写入模式控制寄存器的模式控制数据来替代地选择由这些单元保持的控制过程。

59. 发明授权

US4615005A Data processing apparatus with clock signal control by microinstruction for reduced power consumption and method therefor 失效
标题翻译：具有通过微指令控制时钟信号的数据处理装置，用于降低功耗及其方法
公开(公告)号：US4615005A
公开(公告)日：1986-09-30
申请号：US632820
申请日：1984-07-20
申请人： Hideo Maejima , Koyo Katsura , Toshimasa Kihara , Yasushi Akao
发明人： Hideo Maejima , Koyo Katsura , Toshimasa Kihara , Yasushi Akao
IPC分类号： G06F1/04 , G06F1/32 , G06F9/30 , G06F11/00 , G06F7/38
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/324 , Y02B60/1217
摘要： Disclosed is a method of controlling the supply of a clock signal to a logic circuit, especially, a logic circuit composed of C-MOS gates for further reducing the power consumption. According to the control method, a clock signal supply inhibit instruction is stored, so that, when this instruction is read out, the supply of the clock signal to the logic circuit is inhibited, or its level is fixed at a specific signal level. In response to the application of an interrupt signal, the clock signal having been inhibited to be supplied to the logic circuit starts to be supplied to the logic circuit again. The circuit region or regions for which the supply of the clock signal is to be inhibited can be freely selected for the purpose of control. Thus, the method is especially effective when it is desired to closely control the saving of power consumed by the logic circuit.
摘要翻译：公开了一种控制向逻辑电路提供时钟信号的方法，特别是由用于进一步降低功耗的C-MOS门组成的逻辑电路。根据控制方法，存储时钟信号供给禁止指令，使得当读出该指令时，禁止向逻辑电路提供时钟信号，或者将其电平固定在特定信号电平。响应于中断信号的应用，被禁止提供给逻辑电路的时钟信号开始再次提供给逻辑电路。为了控制，可以自由地选择要禁止提供时钟信号的电路区域。因此，当期望密切控制逻辑电路消耗的功率的节省时，该方法特别有效。

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