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    • 55. 发明授权
    • Test apparatus and test method
    • 试验装置及试验方法
    • US07945826B2
    • 2011-05-17
    • US12487615
    • 2009-06-18
    • Satoshi KamedaMasaru DoiShinya Sato
    • Satoshi KamedaMasaru DoiShinya Sato
    • G11C29/00
    • G11C29/56G06F11/1068G11C29/56008G11C2029/5606
    • Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information. The test apparatus detects whether there is a defect corresponding to each of a plurality of fail conditions, outputs the detection result as a fail signal, and updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to the allocated fail conditions.
    • 提供一种具有坏块存储器的测试装置,用于与被测存储器的块相关联地存储多条故障信息,每条失败信息指示相关块中是否存在缺陷。 测试装置将测试数据序列写入正在测试的存储器的被测页面,读取写入被测页面的测试数据序列,并将读取的数据序列与写入的数据序列进行比较。 该测试装置包括一个分配寄存器,该分配寄存器存储分配信息,用于设置用于判断被测页面中是否存在缺陷的多个故障条件中的哪一个被分配给多个故障信息。 测试装置检测是否存在与多个故障条件中的每一个相对应的缺陷,将检测结果输出为故障信号,并使用故障信号更新与包括被测页的块相关联的多条故障信息 对应于分配的失败条件。
    • 56. 发明授权
    • Test apparatus and test method
    • 试验装置及试验方法
    • US07930614B2
    • 2011-04-19
    • US11714071
    • 2007-03-05
    • Shinya Sato
    • Shinya Sato
    • H03M13/00
    • G11C29/42G11C29/44
    • A test apparatus is provided for testing memory under test which stores a data string including an error correction code in the form of additional data. The test apparatus comprises: a logic comparator which compares each of the data sets included in a data string read out from the memory under test with a corresponding anticipated value created beforehand; a data error count unit which counts the number of data sets that do not match the respective anticipated values; and a defect detection unit which provides a function whereby, in a case that the count value counted by the error count unit exceeds a predetermined upper limit number which is equal to or greater than 1, determination is made that the memory under test is defective.
    • 提供一种测试装置,用于测试测试存储器,该存储器以附加数据的形式存储包括纠错码的数据串。 测试装置包括:逻辑比较器,将包括在从被测存储器读出的数据串中的每个数据集与预先创建的对应的预期值进行比较; 数据错误计数单元,其计数与各个预期值不匹配的数据集的数量; 以及缺陷检测单元,其提供如下功能:在由误差计数单元计数的计数值超过等于或大于1的预定上限值的情况下,确定被测存储器有缺陷。
    • 57. 发明授权
    • Test apparatus
    • 测试仪器
    • US07679372B2
    • 2010-03-16
    • US11945276
    • 2007-11-27
    • Yasushi KuriharaShinya Sato
    • Yasushi KuriharaShinya Sato
    • G01R31/00
    • G01R31/31924G01R31/31926G11C29/56G11C29/56004G11C2029/5602
    • A driver for supplying a test signal to a device under test is shared by a plurality of terminals. In this way, the cost and time required for the test of the device under test can be reduced.A testing apparatus 10 relating to the present invention includes a test signal generating section 130 that generates a test signal to be supplied to a device under test 20, a driver 140 that outputs the test signal, a switch 150 that is disposed on a wire between the driver 140 and a first terminal of the device under test 20, a switch 160 that is disposed on a wire between the driver 140 and a second terminal of the device under test 20, and a connection control section 100 that (i) turns on the switch 150 and turns off the switch 160 when the test signal is supplied to the first terminal of the device under test 20, and (ii) turns off the switch 150 and turns on the switch 160 when the test signal is supplied to the second terminal of the device under test 20.
    • 用于向被测设备提供测试信号的驱动器由多个终端共享。 以这种方式,可以减少被测设备的测试所需的成本和时间。 本发明的测试装置10包括测试信号产生部分130,该测试信号产生部分130产生要提供给测试装置20的测试信号,输出测试信号的驱动器140,设置在线路上的开关150 驱动器140和被测器件20的第一端子,设置在驱动器140和被测器件20的第二端子之间的导线上的开关160以及(i)接通的连接控制部100 当测试信号被提供给被测器件20的第一端子时,开关150断开开关160,并且(ii)当测试信号被提供给第二个时,关断开关150并接通开关160 被测设备的终端20。
    • 60. 发明授权
    • Testing device
    • 测试装置
    • US07359822B2
    • 2008-04-15
    • US11196020
    • 2005-08-03
    • Yuichi FujiwaraShinya Sato
    • Yuichi FujiwaraShinya Sato
    • G06F19/00
    • G11C29/56G11C16/04
    • A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a plurality of instruction codes, a first instruction pipeline operable to generate a condition satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal satisfies the condition based on the plurality of instruction codes, a second instruction pipeline operable to generate a condition non-satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal does not satisfy the condition based on the plurality of instruction codes, and a selection unit operable to select which of the condition satisfaction instruction stream or the condition non-satisfaction instruction stream is supplied to the test pattern outputting unit based on the result decided by the deciding unit.
    • 测试电子设备的测试设备包括:测试模式输出单元,用于向电子设备输出测试模式;判定单元,用于判断来自电子设备的输出信号是否满足预定条件;指令存储单元, 存储多个指令代码;第一指令流水线,其可操作以产生条件满足指令流,所述条件满足指令流包括多个指令,当所述输出信号满足所述条件时,使所述测试图案输出单元输出要提供给所述电子设备的测试图案 基于所述多个指令代码,第二指令流水线,其可操作以产生条件不满足指令流,所述条件不满足指令流包括多个指令,所述多个指令使得所述测试图案输出单元输出所述要提供给所述电子设备的所述测试图案, 不符合条件的 所述多个指令代码,以及选择单元,用于根据由所述判定单元确定的结果,选择所述条件满足指令流或所述条件不满足指令流中的哪一个被提供给所述测试图案输出单元。