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51. 发明授权

US06272619B1 High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US06272619B1
公开(公告)日：2001-08-07
申请号：US09437601
申请日：1999-11-10
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

52. 发明授权

US06263423B1 System and method for translating non-native instructions to native instructions for processing on a host processor 失效
标题翻译：用于将非本机指令转换为本地指令以在主机处理器上进行处理的系统和方法
公开(公告)号：US06263423B1
公开(公告)日：2001-07-17
申请号：US09401860
申请日：1999-09-22
申请人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
发明人： Brett Coon , Yoshiyuki Miyayama , Le Trong Nguyen , Johannes Wang
IPC分类号： G06F930
CPC分类号： G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/30152 , G06F9/30163 , G06F9/30167 , G06F9/3017 , G06F9/30174 , G06F9/30185 , G06F9/3816 , G06F9/382 , G06F9/3853
摘要： A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.
摘要翻译：一种用于从复杂指令流中提取复杂的可变长度计算机指令的系统和方法，每个细分流被分成可变数量的指令字节，并且对齐复杂指令中各个指令的指令字节。系统接收复指令流的一部分，并使用提取移位器从第一指令字节开始提取第一组指令字节。然后将该组指令字节传递到对齐锁存器，在该锁存器中它们对准并输出到下一个指令检测器。下一个指令检测器基于所述指令字节集来确定第一指令的结束。提取移位器用于提取并提供下一组指令字节到对齐移位器，对准移位器对齐并输出下一条指令。然后对复杂指令流中的剩余指令字节重复该过程。孤立的复杂指令被解码成由RISC处理器核心处理的纳米指令。

53. 发明授权

US6128723A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US6128723A
公开(公告)日：2000-10-03
申请号：US309603
申请日：1999-05-11
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统以指定的顺序程序顺序（按顺序）获取多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令并调度用于由功能单元执行无序执行的指令。寄存器文件包括一组由指令执行控制单元用于接收由功能单元产生的数据结果的临时数据寄存器。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

54. 发明授权

US6092181A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US6092181A
公开(公告)日：2000-07-18
申请号：US946078
申请日：1997-10-07
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/40
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

55. 发明授权

US6038654A High performance, superscalar-based computer system with out-of-order instruction execution 失效
公开(公告)号：US6038654A
公开(公告)日：2000-03-14
申请号：US338563
申请日：1999-06-23
申请人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le Trong Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.

56. 发明授权

US5828861A System and method for reducing the critical path in memory control unit and input/output control unit operations 失效
标题翻译：用于减少存储器控制单元和输入/输出控制单元操作中的关键路径的系统和方法
公开(公告)号：US5828861A
公开(公告)日：1998-10-27
申请号：US846231
申请日：1992-03-06
申请人： Yoshiyuki Miyayama , Cheng-Long Tang
发明人： Yoshiyuki Miyayama , Cheng-Long Tang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F12/00 , G06F13/42 , G06F9/00
CPC分类号： G06F13/4243 , G06F9/30145 , G06F9/3824 , G06F9/3842 , G06F9/3867
摘要： A system and method for eliminating the critical path of a processor-based system by sending a signal to transition memory and/or I/O control units to a READ/WRITE state prior to the end of the complete instruction decode. If the decoding phase of the opcode of the instruction reveals that a read-write step is to be carried out wherein memory or an I/O device must be accessed, the processor immediately sends a read-write request to the memory control unit and the I/O control unit prior to decoding the balance of the instruction. Once the balance of the instruction has been decoded and the access location is determined to be in either memory or an I/O device, a cancellation process takes place. In this cancellation process, if the access location is in memory, the I/O unit transitions from the read-write state to an idle state. If, however, the access destination is determined to be an I/O device, the memory control unit transitions from the read-write state to the idle state.
摘要翻译：一种用于通过在完成指令解码结束之前将转换存储器和/或I / O控制单元发送到READ / WRITE状态的信号来消除基于处理器的系统的关键路径的系统和方法。如果指令的操作码的解码阶段显示要进行读写步骤，其中必须存储存储器或I / O设备，则处理器立即向存储器控制单元发送读写请求，并且 I / O控制单元在解码指令的平衡之前。一旦指令的平衡被解码并且确定访问位置在存储器或I / O设备中，则进行取消处理。在该取消处理中，如果访问位置在存储器中，I / O单元从读写状态转换到空闲状态。然而，如果将访问目的地确定为I / O设备，则存储器控制单元从读写状态转换到空闲状态。

57. 发明授权

US5539911A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US5539911A
公开(公告)日：1996-07-23
申请号：US817810
申请日：1992-01-08
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F13/00
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统获取和存储程序指令集。每个指令集包括具有指定的顺序程序顺序（按顺序）的多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令集并且调度用于由功能单元执行无序执行的指令。寄存器文件包括一组临时数据寄存器，由指令执行控制单元用来接收由功能单元产生的数据结果。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

58. 发明授权

US5481685A RISC microprocessor architecture implementing fast trap and exception state 失效
标题翻译： RISC微处理器架构实现快速陷阱和异常状态
公开(公告)号：US5481685A
公开(公告)日：1996-01-02
申请号：US345333
申请日：1994-11-21
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/42 , G06F9/455 , G06F9/46 , G06F9/48 , G06F15/78 , G06F9/40
CPC分类号： G06F9/3865 , G06F15/7842 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
摘要翻译：一种用于微处理器的快速陷阱机制，其中维护一个向量陷阱表，其中包含每个表格条目中的多个指令的空间。当发生快速陷阱时，控制将直接传输到与陷阱号对应的表条目中。陷阱处理程序可以完全位于表条目中，也可以将控制权转移到附加的处理程序代码。

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