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51. 发明授权

US5807776A Method of forming dynamic random access memory circuitry and dynamic random access memory 失效
标题翻译：形成动态随机存取存储器电路和动态随机存取存储器的方法
公开(公告)号：US5807776A
公开(公告)日：1998-09-15
申请号：US727922
申请日：1996-10-09
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L27/12
CPC分类号： H01L27/10861 , H01L27/10829 , H01L27/1203 , H01L28/40
摘要： A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor container openings with insulative material; j) providing a gate dielectric layer atop the SOI layer islands; k) providing conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; l) providing opposing FET source and drain regions within the SOI layer; and m) providing bit lines outwardly of the word lines, the bit lines connecting with selected drain regions.
摘要翻译：形成动态随机存取存储器电路的半导体处理方法包括：a）提供导电电容器单元板基板; b）在电池板上提供电绝缘层; c）在绝缘层上提供半导体材料层，从而限定绝缘体上半导体（SOI）层; d）图案化和蚀刻SOI层以限定岛之间的有源区域岛和隔离沟槽; e）用绝缘材料填充隔离沟; f）提供通过SOI层和绝缘层的电容器开口进入电池板衬底; g）在电容器开口内的电池板衬底上提供电容器电介质层; h）在电容器开口内的电介质层上提供相应的电容器存储节点，各个存储节点与SOI层欧姆连接; i）在提供存储节点之后，用绝缘材料填充电容器容器开口的剩余部分; j）在SOI层岛顶上提供栅介质层; k）在岛上的栅极电介质层和填充的隔离沟槽之上提供导电字线; l）在SOI层内提供相对的FET源极和漏极区域; 并且m）在字线外部提供位线，位线与选择的漏极区域连接。

52. 发明申请

US20110147827A1 Flash memory with partially removed blocking dielectric in the wordline direction 审中-公开
标题翻译：在字线方向上部分去除阻塞电介质的闪存
公开(公告)号：US20110147827A1
公开(公告)日：2011-06-23
申请号：US12655090
申请日：2009-12-23
申请人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
发明人： Fatma Arzum Simsek-Ege , Sanh Tang , Nirmal Ramaswamy , Thomas M. Graettinger , Kyu S. Min , Tejas Krishnamohan , Srivardhan Gowda
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L29/40117 , H01L29/792
摘要： The present disclosure relates generally to the fabrication of non-volatile memory. In at least one embodiment, the present disclosure relates to forming a layered blocking dielectric which has a portion thereof removed in the wordline direction.
摘要翻译：本公开一般涉及非易失性存储器的制造。在至少一个实施例中，本公开涉及形成分层阻挡电介质，其具有沿字线方向的一部分。

53. 发明申请

US20110133266A1 Flash Memory Having a Floating Gate in the Shape of a Curved Section 审中-公开
标题翻译：闪存在曲面形状中具有浮动门
公开(公告)号：US20110133266A1
公开(公告)日：2011-06-09
申请号：US12629992
申请日：2009-12-03
申请人： Sanh Tang , Krishna K. Parat , Haitao Liu
发明人： Sanh Tang , Krishna K. Parat , Haitao Liu
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/11548 , H01L27/11521 , H01L27/11526 , H01L27/11543 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： The floating gate of a flash memory may be formed with a flat lower surface facing a substrate and a curved upper surface facing the control gate. In some embodiments, such a device has improved capacitive coupling to the control gate and reduced capacitive coupling to its neighbors.
摘要翻译：闪存的浮动栅可以形成有面向基板的平坦的下表面和面对控制栅的弯曲的上表面。在一些实施例中，这种器件具有改善的与控制栅极的电容耦合并且减小与其邻居的电容耦合。

54. 发明申请

US20080032494A1 INTERCONNECT STRUCTURES WITH BOND-PADS AND METHODS OF FORMING BUMP SITES ON BOND-PADS 有权
标题翻译：具有粘合剂的互连结构和形成粘结垫的方法
公开(公告)号：US20080032494A1
公开(公告)日：2008-02-07
申请号：US11872607
申请日：2007-10-15
申请人： Sanh Tang , Mark Tuttle , Keith Cook
发明人： Sanh Tang , Mark Tuttle , Keith Cook
IPC分类号： H01L21/441
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0401 , H01L2224/04073 , H01L2224/05018 , H01L2224/05026 , H01L2224/05082 , H01L2224/05181 , H01L2224/05187 , H01L2224/05558 , H01L2224/05559 , H01L2224/05571 , H01L2224/05624 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/0496 , H01L2924/05042 , H01L2924/14 , H01L2924/04941 , H01L2224/05552
摘要： Microelectronic workpieces that have bump sites over bond-pads and methods of fabricating such bump sites. One embodiment of such a workpiece, for example, includes a substrate having a plurality of microelectronic dies comprising integrated circuitry and bond-pads, such as copper bond-pads, electrically coupled to the integrated circuitry. The workpiece further includes (a) a dielectric structure having a plurality of openings with sidewalls projecting from corresponding bond-pads, and (b) a plurality of caps over corresponding bond-pads. The individual caps can include a discrete portion of a barrier layer attached to the bond-pads and the sidewalls of the openings, and a discrete portion of a cap layer on the barrier layer. The caps are electrically isolated from each other and self-aligned with corresponding bond-pads without forming a mask layer over the cap layer.
摘要翻译：在焊盘上具有凸起部位的微电子工件以及制造这种凹凸点的方法。例如，这种工件的一个实施例包括具有多个微电子管芯的衬底，该多个微电子管芯包括集成电路和电耦合到集成电路的接合焊盘，例如铜接合焊盘。工件还包括（a）具有多个开口的电介质结构，其中侧壁从相应的接合焊盘突出，以及（b）在相应的接合焊盘上的多个盖。各个盖可以包括附着到接合焊盘和开口的侧壁的阻挡层的分立部分，以及阻挡层上的覆盖层的离散部分。盖子彼此电隔离并且与相应的接合焊盘自对准，而不在盖层上形成掩模层。

55. 发明申请

US20070224753A1 VERTICAL WRAP-AROUND-GATE FIELD-EFFECT-TRANSISTOR FOR HIGH DENSITY, LOW VOLTAGE LOGIC AND MEMORY ARRAY 有权
标题翻译：用于高密度，低电压逻辑和存储器阵列的垂直封装栅极场效应晶体管
公开(公告)号：US20070224753A1
公开(公告)日：2007-09-27
申请号：US11756800
申请日：2007-06-01
申请人： Sanh Tang , Robert Burke , Anand Srinivasan
发明人： Sanh Tang , Robert Burke , Anand Srinivasan
IPC分类号： H01L21/8238
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10876 , H01L27/10891 , H01L27/1203 , H01L29/42392 , H01L29/78642
摘要： A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
摘要翻译：具有环绕栅极的垂直晶体管和制造这种晶体管的方法。环绕栅极（WAG）垂直晶体管通过其中晶体管的源极，漏极和沟道区域通过制造工艺自动限定和对准而不进行光刻图案化的工艺制造。

56. 发明申请

US20070117381A1 SILICON RICH BARRIER LAYERS FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于集成电路设备的硅胶绝缘层
公开(公告)号：US20070117381A1
公开(公告)日：2007-05-24
申请号：US11625846
申请日：2007-01-23
申请人： Sanh Tang , Chris Braun , Farrell Good
发明人： Sanh Tang , Chris Braun , Farrell Good
IPC分类号： H01L21/8238 , H01L29/76 , H01L21/44
CPC分类号： G11C11/412 , G11C7/02 , H01L21/28061 , H01L21/76829 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L27/11 , H01L27/1104 , H01L29/4941 , Y10S257/903
摘要： Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.
摘要翻译：使用富硅势垒层形成半导体器件和存储单元，以防止掺杂剂从不同掺杂的多晶硅膜扩散到覆盖的导电层或衬底上。可以使用富硅阻挡层来形成多晶硅栅极电极结构。还提供了形成半导体器件和存储单元的方法。

57. 发明申请

US20070022601A1 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices 有权
标题翻译：用于微电子器件的双镶嵌位线结构和制造微电子器件的方法
公开(公告)号：US20070022601A1
公开(公告)日：2007-02-01
申请号：US11542706
申请日：2006-10-03
申请人： Sanh Tang
发明人： Sanh Tang
IPC分类号： H05K3/10
CPC分类号： H01L27/10885 , H01L21/76831 , H01L21/76897 , H01L27/1052 , H01L27/10855 , H01L27/10888 , Y10T29/49147 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49222 , Y10T29/49227
摘要： The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. This embodiment continues by forming a trench through an upper portion of a plurality of the bit line contacts and portions of the dielectric layer between bit line contacts. The trench has a first sidewall and a second sidewall. In certain embodiments, the method continues by fabricating a spacer made from a dielectric material along at least the first sidewall of the trench and then fabricating a bit line in the trench. The bit line is embedded into the bit line contacts. The bit line is electrically coupled to selected bit line contacts, but is electrically insulated from the cell plugs.
摘要翻译：本发明涉及制造用于微电子器件的部件，包括存储器单元或其他部件的微电子器件以及包括存储器件的计算机的方法。例如，一个实施例涉及在工件上制造存储单元的方法，所述工件具有衬底，衬底中的多个有源区和有源区上的介电层。该方法的一个实施例包括在有源区域的第一部分和有源区域的第二部分上的电池插头开口的第一部分上构造电介质层中的位线接触开口。该方法还包括将第一导电材料沉积到位线接触开口中以形成位线接触并进入电池插头开口以形成电池插头。该实施例通过在多个位线触点的上部形成沟槽，并且在位线触点之间形成电介质层的部分。沟槽具有第一侧壁和第二侧壁。在某些实施例中，该方法通过沿沟槽的至少第一侧壁制造由介电材料制成的间隔物，然后在沟槽中制造位线来继续。位线被嵌入到位线接点中。位线电耦合到选定的位线触点，但与电池插头电绝缘。

58. 发明申请

US20060258084A1 Vertical transistors 有权
公开(公告)号：US20060258084A1
公开(公告)日：2006-11-16
申请号：US11491066
申请日：2006-07-21
申请人： Sanh Tang , Gordon Haller
发明人： Sanh Tang , Gordon Haller
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10814 , H01L27/10876 , H01L27/10888 , H01L29/66666
摘要： Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.

59. 发明申请

US20060237847A1 INTEGRATED CIRCUIT INTERCONNECT 有权
标题翻译：集成电路互连
公开(公告)号：US20060237847A1
公开(公告)日：2006-10-26
申请号：US11427746
申请日：2006-06-29
申请人： Martin Roberts , Sanh Tang
发明人： Martin Roberts , Sanh Tang
IPC分类号： H01L23/52
CPC分类号： H01L27/10882 , H01L21/76838 , H01L23/485 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an electrical interconnect overlying a buried contact region of a substrate is characterized by a deposition of a first polycrystalline silicon layer and the patterning and etching of same to form a via. The via is formed in the first polycrystalline silicon layer to expose the substrate and a second polycrystalline silicon layer is formed in the via to contact the substrate. Portions of the second polycrystalline silicon layer overlying the first polycrystalline silicon layer are removed eliminating any horizontal interface between the two polycrystalline silicon layers. The first polycrystalline silicon layer remaining after the etch is then patterned to form an electrical interconnect.
摘要翻译：用于形成覆盖衬底的掩埋接触区域的电互连的方法的特征在于沉积第一多晶硅层及其图案化和蚀刻以形成通孔。通孔形成在第一多晶硅层中以露出衬底，并且在通孔中形成第二多晶硅层以接触衬底。去除覆盖在第一多晶硅层上的第二多晶硅层的部分，消除了两个多晶硅层之间的任何水平界面。然后在蚀刻之后残留的第一多晶硅层被图案化以形成电互连。

60. 发明申请

US20060205135A1 Silicon rich barrier layers for integrated circuit devices 有权
公开(公告)号：US20060205135A1
公开(公告)日：2006-09-14
申请号：US11430792
申请日：2006-05-09
申请人： Sanh Tang , Chris Braun , Farrell Good
发明人： Sanh Tang , Chris Braun , Farrell Good
IPC分类号： H01L21/8238
CPC分类号： G11C11/412 , G11C7/02 , H01L21/28061 , H01L21/76829 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L27/11 , H01L27/1104 , H01L29/4941 , Y10S257/903
摘要： Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.

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