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    • 52. 发明授权
    • Focus detecting device
    • 对焦检测装置
    • US4849782A
    • 1989-07-18
    • US877850
    • 1986-06-24
    • Takeshi KoyamaKeiji Ohtaka
    • Takeshi KoyamaKeiji Ohtaka
    • G02B7/34
    • G02B7/343
    • A focus detecting device having a field lens disposed near the predetermined imaging plane of an objective and a secondary imaging optical system disposed rearwardly of the field lens, whereby a pair of object images based on light beams passing through different portions of the pupil of the objective are formed and the respective object images are detected by photoelectric conversion element rows disposed rearwardly of the secondary imaging optical system to thereby discriminate the focus state of the objective from the amount of relative deviation of the object images is characterized in that a refracting portion for refracting the light beam in the direction of arrangement of the photoelectric conversion elements is provided in the secondary imaging optical system.
    • 一种聚焦检测装置,其具有设置在物镜的预定成像平面附近的场透镜和设置在场透镜后方的二次成像光学系统,由此基于通过目标的瞳孔的不同部分的光束的一对物体图像 并且通过设置在次级成像光学系统的后方的光电转换元件行来检测各个物体图像,从而将物体的聚焦状态与物体图像的相对偏离量相区别,其特征在于折射部分 在二次成像光学系统中设置在光电转换元件的布置方向上的光束。
    • 58. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08373231B2
    • 2013-02-12
    • US12709762
    • 2010-02-22
    • Sukehiro YamamotoTakeshi Koyama
    • Sukehiro YamamotoTakeshi Koyama
    • H01L23/62
    • H01L29/41758H01L27/0266
    • Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions and source regions placed alternately with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: the first metal interconnects formed on the source regions are electrically connected to the second metal interconnect through constant size via-holes, and a ratio between the numbers of the via-holes arranged above each of the source regions is controlled to be less than four according to a distance from the ground potential supply line.
    • 本发明提供一种半导体器件,其包括用于静电放电保护的n型金属氧化物半导体晶体管,其包括彼此交替地放置的漏极区域和源极区域,以及各自设置在每个漏极区域和每个源极区域之间的栅电极,其中 :通过恒定尺寸的通孔,形成在源极区域上的第一金属互连件通过恒定尺寸的通孔电连接到第二金属互连件,并且布置在每个源极区域上方的通孔数量之间的比率被控制为小于4 根据与地电势线的距离。
    • 60. 发明申请
    • MEMORY/LOGIC CONJUGATE SYSTEM
    • 内存/逻辑连接系统
    • US20110255323A1
    • 2011-10-20
    • US12977243
    • 2010-12-23
    • Kanji OtsukaTsuneo ItoYoichi SatoMasahiro YoshidaShigeru YamamotoTakeshi KoyamaYuko TanbaYutaka Akiyama
    • Kanji OtsukaTsuneo ItoYoichi SatoMasahiro YoshidaShigeru YamamotoTakeshi KoyamaYuko TanbaYutaka Akiyama
    • G11C5/06
    • G06F13/4022G11C5/02G11C7/1006G11C2213/71
    • There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
    • 存在带宽瓶颈的问题,因为使用交叉开关来应对规模的增加。 在根据本发明的存储器/逻辑共轭系统的示例中,多个集群存储器芯片,每个集群存储器芯片包括多个集群存储器20,其包括布置在集群中的基本单元10,基本单元10包括存储器电路,以及 控制多个集群存储器的控制器芯片是三维堆叠的,沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由多片11电连接到控制器芯片, 通孔中,任意一个基本单元10通过多轴11从控制器芯片直接访问,从而将真值数据写入其中,从而将任意的基本单元10切换到逻辑电路作为共轭。