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51. 发明授权

US06516405B1 Method and system for safe data dependency collapsing based on control-flow speculation 失效
标题翻译：基于控制流猜测的安全数据依赖性崩溃的方法和系统
公开(公告)号：US06516405B1
公开(公告)日：2003-02-04
申请号：US09475646
申请日：1999-12-30
申请人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
发明人： Stephan J. Jourdan , Freddy Gabbay , Ronny Ronen , Adi Yoaz
IPC分类号： G06F945
CPC分类号： G06F9/30094 , G06F9/383 , G06F9/3832 , G06F9/384 , G06F9/3842 , G06F9/3863
摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.
摘要翻译：本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

52. 发明授权

US06438673B1 Correlated address prediction 有权
标题翻译：相关地址预测
公开(公告)号：US06438673B1
公开(公告)日：2002-08-20
申请号：US09475063
申请日：1999-12-30
申请人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
发明人： Stephan J. Jourdan , Michael Bekerman , Ronny Ronen , Lihu Rappoport
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F12/0862 , G06F2212/6024
摘要： A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.
摘要翻译：具有相关地址预测器的微处理器，以及执行相关地址预测的方法。第一表存储器可以由多个缓冲器入口填充。每个缓冲器条目可以包括基于指令指针存储第一标签的第一缓冲区域和用于存储地址历史的第二缓冲区域。第二表存储器可以由多个链接条目填充。每个链接条目可以包括基于地址历史存储链接标签的第一链接字段和用于存储预测地址的第二链接字段。第一比较器可以与第一表存储器和指令指针输入通信。第二比较器可以与第一表存储器和第二表存储器通信。与第二表存储器通信的输出。

53. 发明授权

US6134643A Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history 失效
标题翻译：使用预取控制器和缓冲器和访问历史的高速缓存行预测和预取的方法和装置
公开(公告)号：US6134643A
公开(公告)日：2000-10-17
申请号：US979575
申请日：1997-11-26
申请人： Gershon Kedem , Ronny Ronen , Adi Yoaz
发明人： Gershon Kedem , Ronny Ronen , Adi Yoaz
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier. At least one prefetch candidate is generated based on the memory request and the access history.
摘要翻译：微处理器包括执行引擎，预测表缓存和预取控制器。执行引擎适于发出存储器请求。存储器请求包括对应于外部主存储器中的行位置的标识符。预测表缓存适于存储定义先前遇到的存储器请求的访问历史的多个条目。预测表缓存由标识符索引。预取控制器适于接收存储器请求，并且基于存储器请求和访问历史来生成至少一个预取候选。用于在微处理器中预取数据的方法包括接收存储器请求。存储器请求包括对应于外部主存储器中的行位置的标识符。将存储器请求与先前遇到的存储器请求的访问历史进行比较。访问历史记录由标识符索引。基于存储器请求和访问历史生成至少一个预取候选。

54. 发明授权

US5701442A Method of modifying an instruction set architecture of a computer processor to maintain backward compatibility 失效
标题翻译：修改计算机处理器的指令集架构以维持向后兼容性的方法
公开(公告)号：US5701442A
公开(公告)日：1997-12-23
申请号：US530614
申请日：1995-09-19
申请人： Ronny Ronen
发明人： Ronny Ronen
IPC分类号： G06F9/318 , G06F9/30
CPC分类号： G06F9/30181 , G06F9/30076
摘要： A method of processor architecture modification includes the step of defining an instruction set architecture for a current generation processor. Reserved within this definition are a set of instructions which perform no-operations (NOPs), have no attached semantics, and do not change any architectural state of the processor. Software code, compatible with the instruction set architecture, is then written for running on the processor. In a next-generation processor, new functionality is added by defining a semantic for one of the NOPs so that programs which utilize the new instruction run on both the current-generation and the next-generation processors.
摘要翻译：处理器架构修改的方法包括为当前一代处理器定义指令集架构的步骤。在此定义中保留一组执行不操作（NOP），没有附加语义的指令，并且不改变处理器的任何架构状态。然后编写与指令集架构兼容的软件代码，用于在处理器上运行。在下一代处理器中，通过为其中一个NOP定义语义来添加新的功能，使得利用新指令的程序在当代和下一代处理器上运行。

55. 发明授权

US10191742B2 Mechanism for saving and retrieving micro-architecture context 有权
公开(公告)号：US10191742B2
公开(公告)日：2019-01-29
申请号：US13993668
申请日：2012-03-30
申请人： Efraim Rotem , Eliezer Weissmann , Boris Ginzburg , Alon Naveh , Nadav Shulman , Ronny Ronen
发明人： Efraim Rotem , Eliezer Weissmann , Boris Ginzburg , Alon Naveh , Nadav Shulman , Ronny Ronen
IPC分类号： G06F9/30 , G06F9/32 , G06F9/34 , G06F9/38 , G06F11/30 , G06F11/34 , G06F1/32 , G06F9/455
摘要： A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

56. 发明授权

US09720730B2 Providing an asymmetric multicore processor system transparently to an operating system 有权
公开(公告)号：US09720730B2
公开(公告)日：2017-08-01
申请号：US13995994
申请日：2011-12-30
申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
IPC分类号： G06F9/46 , G06F9/50 , G06F9/48 , G06F9/30 , G06F15/78
CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.

57. 发明授权

US09348594B2 Core switching acceleration in asymmetric multiprocessor system 有权
标题翻译：非对称多处理器系统中的核心切换加速
公开(公告)号：US09348594B2
公开(公告)日：2016-05-24
申请号：US13992710
申请日：2011-12-29
申请人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
发明人： Koichi Yamada , Boris Ginzburg , Wei Li , Ronny Ronen , Esfir Natanzon , Konstantin Levit-Gurevich , Gadi Haber , Alon Naveh , Eliezer Weissmann , Michael Mishaeli
IPC分类号： G06F9/40 , G06F9/30 , G06F9/50
CPC分类号： G06F9/30181 , G06F9/5044 , G06F9/5094 , Y02D10/22
摘要： An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.
摘要翻译：非对称多处理器系统（ASMP）可以包括实现不同指令集架构并具有不同功率需求的计算核心。在ASMP上执行的程序代码由二进制分析单元进行分析，以确定程序代码调用哪些函数，并选择哪些核执行程序代码或其代码段。可以进行选择以提供程序代码的本地执行，以最小化功耗等等。可以将基于该选择的控制操作插入到程序代码中，形成检测程序代码。然后由ASMP执行检测的程序代码。

58. 发明申请

US20140359629A1 MECHANISM FOR ISSUING REQUESTS TO AN ACCELERATOR FROM MULTIPLE THREADS 审中-公开
标题翻译：用于向多个螺纹加速器发出要求的机制
公开(公告)号：US20140359629A1
公开(公告)日：2014-12-04
申请号：US13992865
申请日：2012-03-30
申请人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
发明人： Ronny Ronen , Boris Ginzburg , Eliezer Weissmann
IPC分类号： G06F9/48 , G06F12/10
摘要： An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.
摘要翻译：描述了具有多个核心的装置，每个核心具有：a）CPU; b）加速器以及c）耦合在CPU和加速器之间的控制器和多个顺序缓冲器。每个命令缓冲区专用于不同的CPU线程。每个订单缓冲区都是保存从其对应的线程发出到加速器的一个或多个请求。控制器用于控制订单缓冲器对加速器的相应请求的发布。

59. 发明申请

US20140082630A1 PROVIDING AN ASYMMETRIC MULTICORE PROCESSOR SYSTEM TRANSPARENTLY TO AN OPERATING SYSTEM 有权
标题翻译：向操作系统提供不对称的多重处理器系统
公开(公告)号：US20140082630A1
公开(公告)日：2014-03-20
申请号：US13995994
申请日：2011-12-30
申请人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
发明人： Boris Ginzburg , Ilya Osadchiy , Ronny Ronen , Eliezer Weissmann , Michael Mishaeli , Alon Naveh , David A. Koufaty , Scott D. Hahn , Tong Li , Avi Mendleson , Eugene Gorbatov , Hisham Abu-Salah , Dheeraj R. Subbareddy , Paolo Narvaez , Aamer Jaleel , Efraim Rotem , Yuval Yosef , Anil Aggarwal , Kenzo Van Craeynest
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F9/30101 , G06F9/4856 , G06F15/7807 , Y02D10/12 , Y02D10/13 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor with first and second groups of cores. The second group can be of a different instruction set architecture (ISA) than the first group or of the same ISA set but having different power and performance support level, and is transparent to an operating system (OS). The processor further includes a migration unit that handles migration requests for a number of different scenarios and causes a context switch to dynamically migrate a process from the second core to a first core of the first group. This dynamic hardware-based context switch can be transparent to the OS. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有第一和第二组核心的多核处理器。第二组可以是与第一组或同一ISA组不同的指令集架构（ISA），但具有不同的功率和性能支持级别，并且对于操作系统（OS）是透明的。处理器还包括迁移单元，其处理针对多个不同场景的迁移请求，并使上下文切换将进程从第二核心动态地迁移到第一组的第一核心。这种基于动态硬件的上下文切换对于操作系统可以是透明的。描述和要求保护其他实施例。

60. 发明授权

US08572358B2 Meta predictor restoration upon detecting misprediction 有权
公开(公告)号：US08572358B2
公开(公告)日：2013-10-29
申请号：US13647153
申请日：2012-10-08
申请人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
发明人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3848
摘要： Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

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