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51. 发明授权

US07754579B2 Method of forming a semiconductor device 失效
标题翻译：形成半导体器件的方法
公开(公告)号：US07754579B2
公开(公告)日：2010-07-13
申请号：US11507647
申请日：2006-08-21
申请人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
发明人： Kimberly Wilson , Hans-Peter Moll , Rolf Weis , Phillip Stopford , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/952
摘要： A method of forming a semiconductor device includes depositing a fill material (4) on a substrate portion (2) and on a dielectric layer (3) being disposed on the substrate (1) and having an opening (10) located above the substrate portion (2), removing the fill material (4) disposed above the dielectric layer (3), thereby leaving an exposed top surface (6) of the dielectric layer (3) and residual fill material (15) within the opening (10), forming a hard mask material (5) on the exposed top surface (6) of the dielectric layer (3) and on the residual fill material (15), patterning the hard mask material (5) for forming a hard mask (25) having trenches (8a, 8b) extending along a lateral direction (X) and exposing portions of the residual fill material (15) adjacent to the dielectric layer (3) and portions of the dielectric layer (3) adjacent to the residual fill material (15), anisotropically etching the dielectric layer (3), the residual fill material (15) and the substrate (1) selectively to the hard mask (5), thereby forming at least a first and a second isolation trench (11a, 11b) extending along the lateral direction (X).
摘要翻译：一种形成半导体器件的方法包括在衬底部分（2）上沉积填充材料（4）和设置在衬底（1）上并具有位于衬底部分上方的开口（10）的介电层（3）（2），去除设置在电介质层（3）上方的填充材料（4），从而在开口（10）内留下介电层（3）的暴露的顶表面（6）和残余填充材料（15）在所述介电层（3）的暴露的顶表面（6）和所述残留填充材料（15）上形成硬掩模材料（5），对所述硬掩模材料（5）进行图案化以形成硬掩模（25），所述硬掩模材料（25）沿着横向方向（X）延伸的沟槽（8a，8b）和暴露与电介质层（3）相邻的残余填充材料（15）的部分和与残余填充材料（15）相邻的介电层（3）的部分），各向异性蚀刻介电层（3），残留填充材料（15）和基板（1）从而形成至少沿横向（X）延伸的第一和第二隔离沟槽（11a，11b）。

52. 发明申请

US20100110753A1 Ferroelectric Memory Cell Arrays and Method of Operating the Same 审中-公开
标题翻译：铁电存储器单元阵列及其操作方法
公开(公告)号：US20100110753A1
公开(公告)日：2010-05-06
申请号：US12262830
申请日：2008-10-31
申请人： Stefan Slesazeck , Rolf Weis , Stefan Jakschik
发明人： Stefan Slesazeck , Rolf Weis , Stefan Jakschik
IPC分类号： G11C11/22 , G11C7/00 , G11C11/34 , H01L21/20
CPC分类号： H01L27/1159 , G11C5/063 , G11C11/22 , G11C11/223 , H01L27/0207 , H01L27/11592 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： An integrated circuit includes a plurality of switching devices, wherein each device includes a gate dielectric capable of assuming at least a first and a second polarization state. The integrated circuit further includes an address circuit configured to control bit lines electrically coupled to first load regions of a load path of the switching devices and a word line electrically coupled to gate electrodes of the switching devices. The address circuit is configured to control a write cycle such that a first voltage is induced at the gate dielectrics of selected ones of the switching devices and a second voltage is induced at the gate dielectrics of non-selected ones of the switching devices. The first voltage suffices to switch the gate dielectrics of the selected devices from the first to the second polarization state and the second voltage does not suffice to switch the gate dielectrics of the non-selected devices.
摘要翻译：集成电路包括多个开关器件，其中每个器件包括能够承受至少第一和第二极化状态的栅极电介质。集成电路还包括地址电路，其被配置为控制电耦合到开关器件的负载路径的第一负载区域的位线和与开关器件的栅极电耦合的字线。地址电路被配置为控制写入周期，使得在所选择的开关器件的栅极电介质处感应出第一电压，并且在非选择的开关器件的栅极电介质处感应出第二电压。第一电压足以将所选择的器件的栅极电介质从第一极化状态切换到第二极化状态，并且第二电压不足以切换未选择器件的栅极电介质。

53. 发明授权

US07687343B2 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US07687343B2
公开(公告)日：2010-03-30
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

54. 发明申请

US20100058018A1 Memory Scheduler for Managing Internal Memory Operations 有权
标题翻译：用于管理内部存储器操作的内存调度器
公开(公告)号：US20100058018A1
公开(公告)日：2010-03-04
申请号：US12202581
申请日：2008-09-02
申请人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
发明人： Michael Kund , Thomas Happ , GillYong Lee , Heinz Hoenigschmid , Rolf Weis , Christoph Ludwig
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C13/0002 , G11C13/0033 , G11C16/3431
摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.
摘要翻译：集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。

55. 发明申请

US20090219496A1 Methods of Double Patterning, Photo Sensitive Layer Stack for Double Patterning and System for Double Patterning 审中-公开
标题翻译：双重图案的方法，双重图案的感光层堆栈和双重图案的系统
公开(公告)号：US20090219496A1
公开(公告)日：2009-09-03
申请号：US12040389
申请日：2008-02-29
申请人： Frank-Michael Kamm , Christoph Noelscher , Stephan Wege , Rolf Weis
发明人： Frank-Michael Kamm , Christoph Noelscher , Stephan Wege , Rolf Weis
IPC分类号： G03B27/42 , G03F7/004 , G03F7/00
CPC分类号： G03F7/095 , G03F7/203 , G03F7/265 , G03F7/70466 , H01L21/0273
摘要： Double patterning a photo sensitive layer stack, is disclosed including providing a substrate being coated with a first and a second photo resist layer, exposing both photo resist layers by employing lithographic projection steps, wherein a second lithographic projection step illuminates a latent image with a focal depth at least partially covering the second photo resist layer.
摘要翻译：公开了双重图案化感光层堆叠，包括提供涂覆有第一和第二光致抗蚀剂层的衬底，通过采用光刻投影步骤曝光两个光致抗蚀剂层，其中第二光刻投影步骤用焦点照射潜像深度至少部分地覆盖第二光致抗蚀剂层。

56. 发明申请

US20090206315A1 INTEGRATED CIRCUIT INCLUDING U-SHAPED ACCESS DEVICE 有权
标题翻译：集成电路，包括U形形式的访问设备
公开(公告)号：US20090206315A1
公开(公告)日：2009-08-20
申请号：US12033519
申请日：2008-02-19
申请人： Rolf Weis , Thomas Happ
发明人： Rolf Weis , Thomas Happ
IPC分类号： H01L45/00
CPC分类号： H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.
摘要翻译：集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。集成电路包括将第一接触与第二接触隔离的自对准电介质材料。

57. 发明申请

US20080296737A1 Methods for Manufacturing a Structure on or in a Substrate, Imaging Layer for Generating Sublithographic Structures, Method for Inverting a Sublithographic Pattern, Device Obtainable by Manufacturing a Structure 有权
标题翻译：用于制造基板上的结构或用于生成亚光刻结构的成像层的方法，用于反转亚光刻图案的方法，通过制造结构可获得的装置
公开(公告)号：US20080296737A1
公开(公告)日：2008-12-04
申请号：US11754813
申请日：2007-05-29
申请人： Rolf Weis , Christoph Noelscher
发明人： Rolf Weis , Christoph Noelscher
IPC分类号： H01L29/06 , H01L21/308
CPC分类号： H01L21/0334 , H01L21/28132 , H01L27/105 , H01L27/1052 , H01L27/10894 , Y10S438/942 , Y10S438/947
摘要： One possible embodiment is a method of manufacturing a structure on or in a substrate with the following stepsa) positioning at least one spacer structure by a spacer technique on the substrate,b) using at least one of the groups of the spacer structure and a structure generated by the spacer structure as a mask for a subsequent particle irradiation step for generating a latent image in the substratec) using the latent image for further processing the substrate.
摘要翻译：一个可能的实施例是在以下步骤中在衬底上或衬底中制造结构的方法：a）通过间隔物技术将至少一个间隔物结构定位在衬底上，b）使用间隔结构的组中的至少一个和由间隔结构生成的结构作为用于随后的用于在基板中产生潜像的颗粒照射步骤的掩模c）使用潜像进一步处理基板。

58. 发明申请

US20080128773A1 Storage capacitor, a memory device and a method of manufacturing the same 有权
标题翻译：存储电容器，存储器件及其制造方法
公开(公告)号：US20080128773A1
公开(公告)日：2008-06-05
申请号：US11633090
申请日：2006-12-04
申请人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
发明人： Peter Moll , Peter Baars , Till Schloesser , Rolf Weis , Klaus Muemmler
IPC分类号： H01L27/108
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L27/10897
摘要： A storage capacitor includes a first capacitor portion and a second capacitor portion, the second capacitor portion being disposed above the first capacitor portion, thereby defining a first direction. The first and the second portions each include a hollow body made of a conductive material, respectively, thereby forming a first capacitor electrode. An upper diameter of each of the hollow bodies is larger than a lower diameter of the hollow body, the diameter being measured perpendicularly with respect to the first direction. The storage capacitor also includes a second capacitor electrode and a dielectric material disposed between the first and the second capacitor electrodes. The storage capacitor also includes an insulating material disposed outside the hollow bodies, and a layer of an insulating material. A lower side of the insulating layer is disposed at a height of an upper side of the first capacitor portion.
摘要翻译：存储电容器包括第一电容器部分和第二电容器部分，第二电容器部分设置在第一电容器部分上方，从而限定第一方向。第一和第二部分分别包括由导电材料制成的中空体，从而形成第一电容器电极。每个中空体的上直径大于中空体的下直径，其直径相对于第一方向垂直地被测量。存储电容器还包括设置在第一和第二电容器电极之间的第二电容器电极和介电材料。存储电容器还包括设置在中空体外部的绝缘材料和绝缘材料层。绝缘层的下侧设置在第一电容器部分的上侧的高度处。

59. 发明申请

US20080001201A1 STORAGE CAPACITOR AND METHOD OF MANUFACTURING A STORAGE CAPACITOR 有权
标题翻译：存储电容器和存储电容器的制造方法
公开(公告)号：US20080001201A1
公开(公告)日：2008-01-03
申请号：US11856409
申请日：2007-09-17
申请人： Rolf Weis
发明人： Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L21/76802 , H01L21/76885 , H01L21/76895 , H01L27/10852 , H01L28/91
摘要： An integrated circuit including a storage capacitor suitable for use in a DRAM cell, as well as to a method of manufacturing such a storage capacitor is disclosed. The storage capacitor is formed at least partially above a semiconductor substrate surface. The invention also includes a memory array employing the storage capacitor.
摘要翻译：公开了一种包括适用于DRAM单元的存储电容器的集成电路，以及制造这种存储电容器的方法。存储电容器至少部分地形成在半导体衬底表面上方。本发明还包括采用存储电容器的存储器阵列。

60. 发明授权

US07301192B2 Dram cell pair and dram memory cell array 失效
标题翻译：戏剧单元对和阵容记忆体单元阵列
公开(公告)号：US07301192B2
公开(公告)日：2007-11-27
申请号：US11222273
申请日：2005-09-08
申请人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Grüning Von Schwerin , Till Schloesser , Rolf Weis
发明人： Johann Harter , Wolfgang Mueller , Wolfgang Bergner , Ulrike Grüning Von Schwerin , Till Schloesser , Rolf Weis
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , G11C11/404 , H01L27/0207 , H01L27/10808 , H01L27/10829 , H01L29/785
摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.
摘要翻译：堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

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