专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US6133129A Method for fabricating a metal structure with reduced length that is beyond photolithography limitations 失效
标题翻译：用于制造超过光刻限制的具有减小的长度的金属结构的方法
公开(公告)号：US6133129A
公开(公告)日：2000-10-17
申请号：US306875
申请日：1999-05-07
申请人： Qi Xiang , Scott A. Bell , Chih-Yuh Yang
发明人： Qi Xiang , Scott A. Bell , Chih-Yuh Yang
IPC分类号： H01L21/28 , H01L21/321 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28123 , H01L21/28079 , H01L21/321 , H01L29/66575 , Y10S438/947
摘要： A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure. The base metal structure has a second predetermined length that is reduced from the first predetermined length when the layer of silicon has consumed into the sidewalls of the base metal structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of silicon deposited on the sidewalls of the base metal structure before the silicidation anneal. After the silicidation anneal, the metal silicide is then removed from the sidewalls of the base metal structure. A remaining portion of the base metal structure, after the metal silicide is removed, forms the metal structure of the present invention having the reduced length that is substantially equal to the second predetermined length. The present invention may be used to particular advantage when the metal structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
摘要翻译：通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的金属结构，其超过了通过光刻可以实现的结构。通常，本发明包括在半导体衬底上形成贱金属结构的步骤。贱金属结构具有由基体金属结构的第一预定长度的端部上的侧壁限定的第一预定长度。本发明还包括在基底金属结构的侧壁上沉积硅层的步骤，并且该硅层具有预定的厚度。硅层在贱金属结构的侧壁处与基体金属结构反应，以在硅化退火中形成金属硅化物，该金属硅化物由在贱金属结构的侧壁处与基体金属结构反应的硅层组成。贱金属结构具有第二预定长度，当硅层在硅化退火之后消耗到基体金属结构的侧壁中时，该第一预定长度从第一预定长度减小。第二预定长度取决于在硅化退火之前沉积在贱金属结构的侧壁上的硅层的预定厚度。在硅化退火之后，然后从基体金属结构的侧壁去除金属硅化物。在金属硅化物被除去之后，母体金属结构的剩余部分形成具有基本上等于第二预定长度的减小的长度的本发明的金属结构。当具有减小的长度的金属结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以被用于特别的优点。

52. 发明授权

US6121123A Gate pattern formation using a BARC as a hardmask 失效
标题翻译：使用BARC作为硬掩模的栅格图案形成
公开(公告)号：US6121123A
公开(公告)日：2000-09-19
申请号：US924573
申请日：1997-09-05
申请人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
发明人： Christopher F. Lyons , Scott A. Bell , Olov Karlsson
IPC分类号： G03F7/09 , H01L21/027 , H01L21/28 , H01L21/3213 , H01L21/3205 , H01L21/4763
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/28123 , H01L21/32139 , Y10S438/952
摘要： A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.
摘要翻译：通过使用SiON膜作为底部抗反射涂层（BARC）并随后作为硬掩模在半导体衬底上形成栅极，以更好地控制通过深UV抗蚀剂掩模定义的栅极的临界尺寸（CD）形成在其上。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层和导电层上的SiON膜。在SiON膜上形成抗蚀剂掩模。 SiON膜改善了抗蚀剂掩模形成过程，然后在随后的蚀刻工艺中用作硬掩模。然后通过依次蚀刻由原始抗蚀剂掩模中的蚀刻窗口所限定的SiON膜和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦浇口已正确成型，然后除去抗蚀剂掩模或SiON膜的任何剩余部分。

53. 发明授权

US6107172A Controlled linewidth reduction during gate pattern formation using an SiON BARC 失效
标题翻译：使用SiON BARC在栅极图案形成期间的受控线宽减小
公开(公告)号：US6107172A
公开(公告)日：2000-08-22
申请号：US905104
申请日：1997-08-01
申请人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
发明人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/302 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/32139 , Y10S438/951 , Y10S438/952
摘要： A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.
摘要翻译：通过产生晶片堆叠形成栅极，该晶片堆叠包括在衬底层上的栅极导电层，在导电层上方沉积SiOxNy层以充当底部抗反射涂层（BARC），并在SiO x N y上形成抗蚀剂掩模层。接下来，抗蚀剂掩模被各向同性地蚀刻以进一步减小在其中形成的栅极图案的临界尺寸，然后蚀刻下面的BARC和晶片叠层以在导电层外形成栅极。

54. 发明授权

US5885902A Integrated arc and polysilicon etching process 失效
标题翻译：集成电弧和多晶硅蚀刻工艺
公开(公告)号：US5885902A
公开(公告)日：1999-03-23
申请号：US964855
申请日：1997-11-05
申请人： Tom Blasingame , Subash Gupta , Scott A. Bell
发明人： Tom Blasingame , Subash Gupta , Scott A. Bell
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L21/00
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/31138 , H01L21/32137 , Y10S438/95 , Y10S438/952
摘要： A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.
摘要翻译：通过用包含氦和/或氮的气体等离子体蚀刻ARC，对多晶硅基本上是惰性的，对多晶硅上的抗反射涂层的复合物进行精确蚀刻以形成多晶硅图案以形成多晶硅图案。

55. 发明授权

US5763327A Integrated arc and polysilicon etching process 失效
公开(公告)号：US5763327A
公开(公告)日：1998-06-09
申请号：US554413
申请日：1995-11-08
申请人： Tom Blasingame , Subash Gupta , Scott A. Bell
发明人： Tom Blasingame , Subash Gupta , Scott A. Bell
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , B44C1/22
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/31138 , H01L21/32137 , Y10S438/95 , Y10S438/952
摘要： A composite of an anti-reflective coating on polysilicon is accurately etched to form a polysilicon pattern by initially etching the ARC with gaseous plasma containing helium and/or nitrogen which is substantially inert with respect to polysilicon.

56. 发明申请

US20080142873A1 INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE 有权
标题翻译：具有金属和半导体门的集成电路系统
公开(公告)号：US20080142873A1
公开(公告)日：2008-06-19
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

57. 发明授权

US07084071B1 Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon 失效
标题翻译：使用多层非晶碳ARC叠层消除线翘曲现象
公开(公告)号：US07084071B1
公开(公告)日：2006-08-01
申请号：US10244650
申请日：2002-09-16
申请人： Srikanteswara Dakshina-Murthy , Scott A. Bell , Richard J. Huang , Richard C. Nguyen , Cyrus E. Tabery
发明人： Srikanteswara Dakshina-Murthy , Scott A. Bell , Richard J. Huang , Richard C. Nguyen , Cyrus E. Tabery
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/823828
摘要： A method of producing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate and providing an amorphous carbon layer over the polysilicon material layer. The amorphous carbon layer comprises at least one undoped amorphous carbon layer and at least one doped amorphous carbon layer. A portion of the amorphous carbon layer is removed to form a hard mask, and the polysilicon material layer is etched according to the hard mask to form a line of polysilicon material.
摘要翻译：制造集成电路的方法包括在半导体衬底上提供多晶硅材料层，并在多晶硅材料层上提供无定形碳层。无定形碳层包括至少一个未掺杂的无定形碳层和至少一个掺杂的无定形碳层。去除非晶碳层的一部分以形成硬掩模，并且根据硬掩模蚀刻多晶硅材料层以形成多晶硅材料线。

58. 发明授权

US07077291B1 Package assembly with foamed topping 失效
标题翻译：包装组装与泡沫顶部
公开(公告)号：US07077291B1
公开(公告)日：2006-07-18
申请号：US10407786
申请日：2003-04-07
申请人： Scott A. Bell , James E. Hawes
发明人： Scott A. Bell , James E. Hawes
IPC分类号： B65D47/04
CPC分类号： B65D51/2828 , B65D85/73
摘要： The present invention provides a package assembly that incorporates a foamable topping under pressure and provides the consumer with a fresh, foamed topping when the package is opened. In one version, the topping material is carried under pressure on top of the liquid contents of the package, and foams when the package is opened. In other versions the topping is carried within the cap or cover of the package, and is selectively dispensed by the consumer after the package has been opened.
摘要翻译：本发明提供了一种包装组件，其在压力下结合有可起泡的顶部，并且当包装打开时向消费者提供新鲜的起泡顶部。在一个版本中，顶部材料在压力下承载在包装的液体内容物的顶部，并且当包装打开时发泡。在其他形式中，顶部装载在包装的盖子或盖子内，并且在包装被打开之后由消费者选择性地分配。

59. 发明授权

US06884733B1 Use of amorphous carbon hard mask for gate patterning to eliminate requirement of poly re-oxidation 有权
标题翻译：使用无定形碳硬掩模进行栅极图案化，以消除多重再氧化的需要
公开(公告)号：US06884733B1
公开(公告)日：2005-04-26
申请号：US10215173
申请日：2002-08-08
申请人： Srikanteswara Dakshina-Murthy , Scott A. Bell , David E. Brown , Philip A. Fisher
发明人： Srikanteswara Dakshina-Murthy , Scott A. Bell , David E. Brown , Philip A. Fisher
IPC分类号： H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337 , H01L21/28123
摘要： A method of producing an integrated circuit eliminates the need to re-oxidize polysilicon gate conductors and lines prior to removal of a hard mask used to form the gate conductors. A layer of polysilicon is provided above a semiconductor substrate. The layer of polysilicon is then doped. A mask material comprising amorphous carbon is provided above the layer of polysilicon, and the layer of mask material is patterned to form a mask. A portion of the layer of polysilicon is removed according to the mask, and the mask is removed.
摘要翻译：制造集成电路的方法消除了在去除用于形成栅极导体的硬掩模之前再次氧化多晶硅栅极导体和线的需要。在半导体衬底之上设置多晶硅层。然后掺杂多晶硅层。包含无定形碳的掩模材料设置在多晶硅层上方，并且掩模材料层被图案化以形成掩模。根据掩模去除多晶硅层的一部分，并且去除掩模。

60. 发明授权

US06740566B2 Ultra-thin resist shallow trench process using high selectivity nitride etch 有权
标题翻译：使用高选择性氮化物蚀刻的超薄抗蚀剂浅沟槽工艺
公开(公告)号：US06740566B2
公开(公告)日：2004-05-25
申请号：US09398641
申请日：1999-09-17
申请人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
发明人： Christopher F. Lyons , Scott A. Bell , Harry J. Levinson , Khanh B. Nguyen , Fei Wang , Chih Yuh Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.
摘要翻译：在一个实施例中，本发明涉及一种形成浅沟槽的方法，包括以下步骤：在半导体衬底上提供包括阻挡氧化物层的半导体衬底，以及在阻挡氧化物层上方的氮化物层; 在所述氮化物层上沉积超薄光致抗蚀剂，所述超薄光致抗蚀剂具有约2,000或更小的厚度; 图案化超薄光致抗蚀剂以暴露氮化物层的一部分并且限定用于浅沟槽的图案; 用具有至少约10:1的氮化物：光致抗蚀剂选择性的蚀刻剂蚀刻氮化物层的暴露部分以暴露部分阻挡氧化物层; 蚀刻阻挡氧化物层的暴露部分以暴露半导体衬底的一部分; 并蚀刻半导体衬底的暴露部分以提供浅沟槽。在另一个实施例中，该方法还包括将绝缘填充材料沉积到浅沟槽中以提供浅沟槽隔离区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式