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51. 发明授权

US08703572B2 Embeded DRAM cell structures with high conductance electrodes and methods of manufacture 有权
标题翻译：具有高电导电极的嵌入式DRAM单元结构和制造方法
公开(公告)号：US08703572B2
公开(公告)日：2014-04-22
申请号：US13269955
申请日：2011-10-10
申请人： Veeraraghavan S. Basker , Richard Q. Williams
发明人： Veeraraghavan S. Basker , Richard Q. Williams
IPC分类号： H01L21/331
CPC分类号： H01L28/60 , H01L27/108 , H01L27/10861 , H01L28/91 , H01L29/66181 , H01L29/945
摘要： A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.
摘要翻译：方法和结构针对具有高电导电极的eDRAM细胞。该方法包括在半导体衬底上形成上层并在上层形成开口。该方法还包括在半导体衬底中形成与开口对准的沟槽。该方法还包括通过将具有电偏压的金属水溶液施加到半导体衬底的背面而在沟槽的所有暴露表面上形成金属板。

52. 发明申请

US20120210283A1 ANALYSIS OF COMPENSATED LAYOUT SHAPES 失效
标题翻译：补偿布局形状分析
公开(公告)号：US20120210283A1
公开(公告)日：2012-08-16
申请号：US13026451
申请日：2011-02-14
申请人： Hongmei Li , Richard Q. Williams
发明人： Hongmei Li , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5068
摘要： The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.
摘要翻译：本公开涉及补偿布局形状的分析。根据实施例的方法包括：使用铲斗结构分析半导体布局，所述布局包括半导体器件; 以及将图案模板应用到所述桶结构的内容以识别与所述半导体器件相邻的形状; 其中，图案模板是从布局基本原理中导出的。

53. 发明申请

US20120185812A1 SYSTEM, METHOD AND PROGRAM STORAGE DEVICE FOR DEVELOPING CONDENSED NETLISTS REPRESENTATIVE OF GROUPS OF ACTIVE DEVICES IN AN INTEGRATED CIRCUIT AND FOR MODELING THE PERFORMANCE OF THE INTEGRATED CIRCUIT BASED ON THE CONDENSED NETLISTS 有权
标题翻译：系统，方法和程序存储设备，用于开发集成电路中的主动设备集中的简明网络代表，并用于基于简明网络来建模集成电路的性能
公开(公告)号：US20120185812A1
公开(公告)日：2012-07-19
申请号：US13005599
申请日：2011-01-13
申请人： Yanqing Deng , Paul A. Hyde , James M. Johnson , Todd G. McKenzie , Scott K. Springer , Richard Q. Williams
发明人： Yanqing Deng , Paul A. Hyde , James M. Johnson , Todd G. McKenzie , Scott K. Springer , Richard Q. Williams
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.
摘要翻译：一种用于开发集成电路内的子电路的精简网表的系统和方法，以及基于精简网表而不是完整的网表来对集成电路的性能进行建模。 IC布局被分割成多个子电路，每个子电路包括通过类似的电阻网络连接到（即共享）相同的电子电路终端的给定类型的有源设备中的一个或多个的组它们受到大致相同的总体组合寄生电阻）。从布局中提取与子电路对应的完整网表，并进行浓缩。每个浓缩网表列出了子电路中的有源器件和电阻网络所呈现的性能变化（例如，作为工作电源电压，工作温度以及任选的自发热和/或应力的变化的函数）。然后在集成电路的工作温度和工作电源电压的全范围内模拟子电路的精简网表，以便为集成电路生成性能模型。

54. 发明授权

US08037433B2 System and methodology for determining layout-dependent effects in ULSI simulation 有权
标题翻译：用于确定ULSI仿真中与布局有关的影响的系统和方法
公开(公告)号：US08037433B2
公开(公告)日：2011-10-11
申请号：US12196471
申请日：2008-08-22
申请人： Dureseti Chidambarrao , Tong Li , Richard Q. Williams , David W. Winston
发明人： Dureseti Chidambarrao , Tong Li , Richard Q. Williams , David W. Winston
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A layout of a semiconductor circuit is analyzed to calculate layout-dependant parameters that can include a mobility shift and a threshold voltage shift. Layout-dependant effects that affect the layout dependant parameters may include stress effects, rapid thermal anneal (RTA) effects, and lithographic effects. Intrinsic functions that do not reflect the layout-dependant effects are calculated, followed by calculation of scaling modifiers based on the layout-dependant parameters. A model output function that reflects the layout-dependant effects is obtained by multiplication of each of the intrinsic functions with a corresponding scaling parameter.
摘要翻译：分析半导体电路的布局以计算可以包括迁移率偏移和阈值电压偏移的依赖于布局的参数。影响依赖于布局的参数的依赖于布局的效应可能包括应力影响，快速热退火（RTA）效应和平版印刷效应。计算不反映与布局有关的影响的内在函数，然后根据与布局相关的参数计算缩放修正符号。通过将每个内在函数与相应的缩放参数相乘来获得反映与布局相关的效应的模型输出函数。

55. 发明授权

US07627840B2 Method for soft error modeling with double current pulse 失效
标题翻译：双电流脉冲软误差建模方法
公开(公告)号：US07627840B2
公开(公告)日：2009-12-01
申请号：US11457174
申请日：2006-07-13
申请人： A J Kleinosowski , Philip J. Oldiges , Paul M. Solomon , Richard Q. Williams
发明人： A J Kleinosowski , Philip J. Oldiges , Paul M. Solomon , Richard Q. Williams
IPC分类号： G06F17/50 , H01L29/94
CPC分类号： G06F17/5036 , G01R31/31816 , G01R31/318357
摘要： A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.
摘要翻译：在逻辑电路中对软错误进行建模的方法使用在设备的源极和漏极处插入的两个单独的电流源来模拟由例如α粒子撞击引起的单个事件不正常（SEU）。在nfet实现中，电流从源极或漏极流向器件的主体。具有已知幅度的电流波形在电流源处被注入，同时模拟逻辑电路的操作，并且根据模拟操作确定逻辑电路的状态。可以独立调整电流波形的幅度。模拟器监视设备的状态，并在转换发生时创建日志条目。逻辑电路中的其他器件可以重复该过程，以提供电路对软错误的敏感性的整体表征。

56. 发明授权

US07579655B2 Transistor structure having interconnect to side of diffusion and related method 失效
标题翻译：具有与扩散侧相互连接的晶体管结构及相关方法
公开(公告)号：US07579655B2
公开(公告)日：2009-08-25
申请号：US11275475
申请日：2006-01-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： H01L29/76
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823871 , H01L29/665 , H01L29/66636 , H01L29/66772
摘要： A transistor structure is disclosed including at least one transistor including a diffusion and an interconnect electrically connected to a side of the diffusion and a conductor in electrical contact with the interconnect. The low-resistivity local interconnect is advantageous for use with stressed liner films since a conductor can contact the interconnect at a distance from the diffusion, thus allowing electrical contact without having to interrupt the stress liner film where it is most effective. Several embodiments of methods of electrically connecting a diffusion to an interconnect are also disclosed.
摘要翻译：公开了一种晶体管结构，其包括至少一个晶体管，其包括扩散和电连接到扩散侧的互连和与互连电接触的导体。低电阻率局部互连有利于与应力衬垫膜一起使用，因为导体可以在距离扩散一定距离处接触互连，从而允许电接触，而不必中断其中最有效的应力衬垫膜。还公开了将扩散电连接到互连的方法的几个实施例。

57. 发明授权

US07512908B2 Method and apparatus for improving SRAM cell stability by using boosted word lines 失效
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US07512908B2
公开(公告)日：2009-03-31
申请号：US11450610
申请日：2006-06-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G06F17/50 , G06F9/45 , G11C16/06 , G11C7/00 , G11C8/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

58. 发明授权

US07327008B2 Structure and method for mixed-substrate SIMOX technology 失效
标题翻译：混合底物SIMOX技术的结构与方法
公开(公告)号：US07327008B2
公开(公告)日：2008-02-05
申请号：US10905857
申请日：2005-01-24
申请人： Richard Q. Williams
发明人： Richard Q. Williams
IPC分类号： H01L29/00
CPC分类号： H01L21/76243
摘要： The present invention provides a semiconductor structure that includes a substrate having a crystal lattice; a first structure formed in a first region of the substrate, the first structure includes at least a heterostructure that generates a lattice stress in said crystal lattice in the first region; and a second structure surrounding the first structure for preventing lattice stress from propagating outward from the first region of the substrate. The present invention also provides various methods for forming the semiconductor structure as well as other like structures.
摘要翻译：本发明提供一种包括具有晶格的基板的半导体结构; 形成在所述基板的第一区域中的第一结构，所述第一结构至少包括在所述第一区域中在所述晶格中产生晶格应力的异质结构; 以及围绕所述第一结构的第二结构，用于防止晶格应力从所述衬底的所述第一区域向外传播。本发明还提供了用于形成半导体结构以及其它类似结构的各种方法。

59. 发明申请

US20070291528A1 Method and apparatus for improving SRAM cell stability by using boosted word lines 失效
标题翻译：通过使用升压字线来提高SRAM单元稳定性的方法和装置
公开(公告)号：US20070291528A1
公开(公告)日：2007-12-20
申请号：US11450610
申请日：2006-06-09
申请人： Hussein I. Hanafi , Richard Q. Williams
发明人： Hussein I. Hanafi , Richard Q. Williams
IPC分类号： G11C11/00 , G11C8/00 , G11C7/00
CPC分类号： G11C7/02 , G11C8/08 , G11C11/413
摘要： The present invention relates to methods and apparatus for improving the stability of static random access memory (SRAM) cells by using boosted word lines. Specifically, a boosted word line voltage (Vdd′) is applied to the word line of a selected SRAM cell, while such a boosted word line voltage (Vdd′) is sufficiently higher than the power supply voltage (Vdd) of the SRAM cell so as to improve the cell stability to a desired level. Specifically, a specific boosted word line voltage is predetermined for each SRAM cell based on the specific cell configuration, by using a circuit simulation program, such as the BERKELEY-SPICE simulation program. A boost voltage generator is then used to apply the predetermined boosted word line voltage to the selected SRAM cell.
摘要翻译：本发明涉及通过使用增强字线来提高静态随机存取存储器（SRAM）单元的稳定性的方法和装置。具体地说，将升压的字线电压（Vdd'）施加到所选择的SRAM单元的字线，而这样的升压字线电压（Vdd'）比SRAM单元的电源电压（Vdd）充分高以将细胞稳定性提高到所需水平。具体地，通过使用例如BERKELEY-SPICE仿真程序的电路仿真程序，基于特定单元配置为每个SRAM单元预定特定的升压字线电压。然后使用升压电压发生器将预定的升压字线电压施加到所选择的SRAM单元。

60. 发明授权

US06433985B1 ESD network with capacitor blocking element 有权
标题翻译：具有电容器阻塞元件的ESD网络
公开(公告)号：US06433985B1
公开(公告)日：2002-08-13
申请号：US09476244
申请日：1999-12-30
申请人： Steven H. Voldman , Richard Q. Williams
发明人： Steven H. Voldman , Richard Q. Williams
IPC分类号： H02H322
CPC分类号： H01L27/0251 , H02H9/046
摘要： An ESD protection network is described which prevents high voltage oxide stress. The network consists of a filter network (such as a blocking capacitor) and diode protection elements. The filter network can be designed for several types of ESD protection functions. It can be designed to provide voltage reduction for ESD pulses, and to selectively block the frequency components of ESD pulses.
摘要翻译：描述了ESD保护网络，其防止高电压氧化物应力。网络由滤波网络（如隔离电容器）和二极管保护元件组成。滤波器网络可以设计用于几种类型的ESD保护功能。它可以设计用于为ESD脉冲提供电压降低，并有选择地阻断ESD脉冲的频率分量。

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