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51. 发明授权

US08080439B2 Method of making a vertical phase change memory (PCM) and a PCM device 有权
标题翻译：制造垂直相变存储器（PCM）和PCM装置的方法
公开(公告)号：US08080439B2
公开(公告)日：2011-12-20
申请号：US12039371
申请日：2008-02-28
申请人： Arturo M. Martinez, Jr. , Rajesh A. Rao
发明人： Arturo M. Martinez, Jr. , Rajesh A. Rao
IPC分类号： H01L21/00 , H01L21/06 , H01L21/8234 , H01L21/20
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , Y10T428/24479
摘要： A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
摘要翻译：制造相变随机存取存储器（PCM）装置的方法包括形成包括加热器层，相变材料层和顶部电极层的PCM堆叠。顶层保护层形成在PCM叠层上。然后将顶部保护层和PCM堆叠的第一部分图案化，其中PCM堆叠的第一部分排除加热器层。沿图案化的顶部保护层和PCM堆叠的第一部分的侧壁形成侧壁保护特征。使用（i）侧壁保护特征和（ii）图案化顶部保护层和PCM堆叠的第一部分一起作为掩模来蚀刻加热器层，以形成PCRAM堆叠的自对准加热器层底部电极，由此完成 PCRAM设备的存储器位。

52. 发明申请

US20090273013A1 METHOD OF FORMING A SPLIT GATE MEMORY DEVICE AND APPARATUS 有权
标题翻译：形成分离栅存储器件和装置的方法
公开(公告)号：US20090273013A1
公开(公告)日：2009-11-05
申请号：US12112664
申请日：2008-04-30
申请人： Brian A. Winstead , Rajesh A. Rao , Spencer E. Williams
发明人： Brian A. Winstead , Rajesh A. Rao , Spencer E. Williams
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L27/11573 , H01L27/11526 , H01L27/11531 , H01L27/11541 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348
摘要： A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.
摘要翻译：分离栅极存储器件具有覆盖衬底的第一部分的具有第一功函数的选择栅极。具有第二功函数的控制栅极覆盖靠近第一部分的衬底的第二部分。当分闸存储器件的多数载流子是电子时，第一功函数大于第二功函数。当分闸门存储器件的多数载体是孔时，第一功函数小于第二功函数。衬底中的第一和第二电流电极被控制栅极和选择栅极之下的沟道分开。控制栅极和选择栅极的不同工作功能导致每个栅极的不同阈值电压以优化器件性能。对于N沟道器件，选择栅极为P电导率，控制栅极为N电导率。

53. 发明申请

US20090220744A1 METHOD OF MAKING A VERTICAL PHASE CHANGE MEMORY (PCM) AND A PCM DEVICE 有权
标题翻译：制造垂直相变记忆体（PCM）和PCM装置的方法
公开(公告)号：US20090220744A1
公开(公告)日：2009-09-03
申请号：US12039371
申请日：2008-02-28
申请人： Arturo M. Martinez, JR. , Rajesh A. Rao
发明人： Arturo M. Martinez, JR. , Rajesh A. Rao
IPC分类号： B32B3/00 , H01B13/00
CPC分类号： H01L45/06 , G11C13/0004 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675 , Y10T428/24479
摘要： A method of making a phase change random access memory (PCM) device comprises forming a PCM stack that includes a heater layer, phase change material layer, and a top electrode layer. A top protection layer is formed overlying the PCM stack. The top protection layer and a first portion of the PCM stack are then patterned, wherein the first portion of the PCM stack excludes the heater layer. A sidewall protection feature is formed along a sidewall of the patterned top protection layer and first portion of the PCM stack. The heater layer is etched using (i) the sidewall protection feature and (ii) the patterned top protection layer and first portion of the PCM stack collectively as a mask to form a self-aligned heater layer bottom electrode of the PCRAM stack, thereby completing a memory bit of the PCRAM device.
摘要翻译：制造相变随机存取存储器（PCM）装置的方法包括形成包括加热器层，相变材料层和顶部电极层的PCM堆叠。顶层保护层形成在PCM叠层上。然后将顶部保护层和PCM堆叠的第一部分图案化，其中PCM堆叠的第一部分排除加热器层。沿图案化的顶部保护层和PCM堆叠的第一部分的侧壁形成侧壁保护特征。使用（i）侧壁保护特征和（ii）图案化顶部保护层和PCM堆叠的第一部分一起作为掩模来蚀刻加热器层，以形成PCRAM堆叠的自对准加热器层底部电极，由此完成 PCRAM设备的存储器位。

54. 发明授权

US06969883B2 Non-volatile memory having a reference transistor 有权
标题翻译：具有参考晶体管的非易失性存储器
公开(公告)号：US06969883B2
公开(公告)日：2005-11-29
申请号：US10950855
申请日：2004-09-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C5/00 , G11C16/28 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/28 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

55. 发明授权

US07265059B2 Multiple fin formation 有权
标题翻译：多鳍形成
公开(公告)号：US07265059B2
公开(公告)日：2007-09-04
申请号：US11240243
申请日：2005-09-30
申请人： Rajesh A. Rao , Leo Mathew
发明人： Rajesh A. Rao , Leo Mathew
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L29/66795 , H01L29/785
摘要： A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.
摘要翻译： FinFET包括多个半导体鳍片。在半导体层上形成图案特征（例如最小光刻尺寸和间距）。在翅片形成的一个示例中，与这些图案化特征的侧面相邻地形成第一组侧壁间隔物。不同材料的第二组侧壁间隔件邻近第一组侧壁间隔件的侧面形成。除去第一组侧壁间隔物，留下第二组侧壁间隔物与图案化特征物间隔开。第二组侧壁间隔物和图案化特征都用作蚀刻的掩模，其使得根据第二组侧壁间隔物和图案化特征使半导体鳍状物图案化。这些产生的具有亚光刻间距的半导体散热片然后用于FinFET晶体管的通道。

56. 发明授权

US06955967B2 Non-volatile memory having a reference transistor and method for forming 有权
标题翻译：具有参考晶体管的非易失性存储器及其形成方法
公开(公告)号：US06955967B2
公开(公告)日：2005-10-18
申请号：US10609361
申请日：2003-06-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C5/00 , G11C16/28 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/28 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11573
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

57. 发明授权

US06839280B1 Variable gate bias for a reference transistor in a non-volatile memory 有权
标题翻译：非易失性存储器中的参考晶体管的可变栅极偏置
公开(公告)号：US06839280B1
公开(公告)日：2005-01-04
申请号：US10609359
申请日：2003-06-27
申请人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
发明人： Gowrishankar L. Chindalore , Rajesh A. Rao , Jane A. Yater
IPC分类号： G11C20060101 , G11C11/34 , G11C16/00 , G11C16/06 , G11C16/28 , H01L21/28 , H01L21/8247
CPC分类号： B82Y10/00 , G11C16/28 , G11C2216/06 , H01L21/28273 , H01L27/11531
摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.
摘要翻译：非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移，51,53）。提供读控制电路（42）以偏置参考晶体管（46）的栅极。读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

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