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51. 发明申请

US20100123612A1 ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND DEVICE 审中-公开
标题翻译：模拟到数字转换电路和器件
公开(公告)号：US20100123612A1
公开(公告)日：2010-05-20
申请号：US12622166
申请日：2009-11-19
申请人： Marco Zamprogno , Federico Guanziroli , Germano Nicollini , Pierangelo Confalonieri
发明人： Marco Zamprogno , Federico Guanziroli , Germano Nicollini , Pierangelo Confalonieri
IPC分类号： H03M1/34
CPC分类号： H03F3/505 , H03F2200/375 , H03F2200/447 , H03F2200/453 , H03F2203/5031 , H03M1/089 , H03M1/12
摘要： An analog-to-digital conversion circuit and device having an input stage arranged to receive an input signal and to provide an output analog signal as a function of the input signal; an analog-to-digital conversion block arranged to receive the output analog signal and to provide a respective output digital signal. The input stage includes a first voltage buffer arranged to provide the output analog signal to the conversion block as the translation of the input signal of an amount equal to a translation voltage; a second voltage buffer arranged to provide a first reference signal to the conversion block that is representative of the translation of a first reference voltage of an amount equal to the translation voltage, so that the conversion block stores the input signal as the difference of the input signal and the first reference voltage regardless of the translation voltage.
摘要翻译：一种具有输入级的模拟 - 数字转换电路和器件，其被布置成接收输入信号并提供作为输入信号的函数的输出模拟信号; 一个模拟 - 数字转换块，用于接收输出模拟信号并提供相应的输出数字信号。输入级包括第一电压缓冲器，其布置成将输出模拟信号提供给转换块，作为等于平移电压的量的输入信号的转换; 第二电压缓冲器，其被布置为向所述转换块提供表示等于所述平移电压的量的第一参考电压的转换的第一参考信号，使得所述转换块将所述输入信号存储为所述输入的差信号和第一个参考电压，无论平移电压如何。

52. 发明申请

US20090051401A1 CALIBRATION CIRCUIT FOR AN ADJUSTABLE CAPACITANCE 有权
标题翻译：用于可调节电容的校准电路
公开(公告)号：US20090051401A1
公开(公告)日：2009-02-26
申请号：US12035235
申请日：2008-02-21
申请人： Pierangelo Confalonieri , Riccardo Martignone , Germano Nicollini
发明人： Pierangelo Confalonieri , Riccardo Martignone , Germano Nicollini
IPC分类号： H03L5/00
CPC分类号： H03H7/0153 , H03H1/02 , H03H2210/021 , H03H2210/043
摘要： A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps. The calibration circuit includes a controllable capacitance for receiving a control signal and including an array of switched capacitors selectively activated by the control signal to connect to a first common node that conducts a voltage value depending on the total capacitance value of the activated capacitors; an assessment unit for comparing this voltage value with a reference voltage to output a logic signal that can transition between first and second logic levels; a control and timing unit to receive the logic signal and change the control signal to carry out a subsequent calibration step that is provided at the end of the integration interval during a comparison interval of a preset duration, which allows a transition of the logic signal to occur prior to the beginning of the consecutive calibration step.
摘要翻译：一种用于校准具有取决于可调电容的时间常数的电路的可调电容的校准电路，所述校准电路产生用于校准电容的校准信号，并且包括适于在几个连续步骤中执行校准循环的校准环路。校准电路包括用于接收控制信号并包括由控制信号选择性激活的开关电容阵列的可控电容，以连接到第一公共节点，该第一公共节点根据所激活的电容器的总电容值传导电压值; 评估单元，用于将该电压值与参考电压进行比较，以输出可在第一和第二逻辑电平之间转换的逻辑信号; 控制和定时单元，用于接收逻辑信号并改变控制信号，以执行在预设持续时间的比较间隔期间在积分间隔结束时提供的随后的校准步骤，这允许将逻辑信号转换为在连续校准步骤开始之前发生。

53. 发明授权

US07283005B2 Clock-pulse generator circuit 失效
标题翻译：时钟脉冲发生器电路
公开(公告)号：US07283005B2
公开(公告)日：2007-10-16
申请号：US11055539
申请日：2005-02-09
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03K3/03
CPC分类号： H03H11/26 , H03K5/04 , H03K5/133 , H03K2005/00071 , H03K2005/00123 , H03K2005/00143 , H03K2005/00156 , H03K2005/00195
摘要： The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.
摘要翻译：电路包括第一环形振荡器，其包括奇数个反相元件，延迟元件和输出端子; 延迟元件相对于输入脉冲的预定边缘以相对于输入脉冲的另一边缘基本上没有时间延迟的预定时间延迟在其输入端响应脉冲。为了避免启动瞬变并产生可以容易地修改的占空比的脉冲，该电路包括具有连接到第一振荡器的输出端的输出端的第二环形振荡器和具有连接到第一振荡器的输出端的双稳态逻辑电路，连接到第一和第二振荡器的公共输出端的输出端子。第一振荡器的反相元件和第二振荡器的反相元件中的至少一个的至少一个构成双稳态逻辑电路的一部分。

54. 发明申请

US20050258998A1 Switched capacitance circuit and analog/digital converter including said circuit 有权
标题翻译：开关电容电路和包括所述电路的模拟/数字转换器
公开(公告)号：US20050258998A1
公开(公告)日：2005-11-24
申请号：US11113954
申请日：2005-04-25
申请人： Pierangelo Confalonieri , Marco Zamprogno
发明人： Pierangelo Confalonieri , Marco Zamprogno
IPC分类号： G11C27/02 , H03H19/00 , H03K5/24 , H03M1/00 , H03M1/06 , H03M1/12 , H03M1/46
CPC分类号： G11C27/026 , G11C27/024 , H03H19/004 , H03K5/2481 , H03K5/249 , H03M1/0682 , H03M1/468
摘要： A switched capacitance circuit including: a switched capacitance section, capable of receiving as input a signal and carrying out a sampling of said signal, the section comprising at least one group of capacitors each of which has a terminal connected to a common node; at least an operational stage including at least an input terminal connected to said common node, the operational stage providing a current to said common node for charging said group of capacitors during a sampling time interval of said signal. The circuit further includes an auxiliary circuit connected to said common node and capable of being activated/deactivated by an enabling signal for injecting a further current into said common node and increasing the current provided to said common node during at least one time interval equal to a fraction of said sampling interval.
摘要翻译：一种开关电容电路，包括：开关电容部分，其能够接收信号并执行所述信号的采样，所述部分包括至少一组电容器，每个电容器的一组电容器具有连接到公共节点的端子; 至少包括连接到所述公共节点的输入端的操作级，所述操作级在所述信号的采样时间间隔期间向所述公共节点提供电流，以对所述电容器组进行充电。该电路还包括连接到所述公共节点的辅助电路，并且能够通过用于将另外的电流注入到所述公共节点中的使能信号来激活/去激活，并且在至少等于一个等待时间间隔的至少一个时间间隔期间增加提供给所述公共节点的电流所述采样间隔的分数。

55. 发明授权

US06720903B2 Method of operating SAR-type ADC and an ADC using the method 有权
标题翻译：使用该方法操作SAR型ADC和ADC的方法
公开(公告)号：US06720903B2
公开(公告)日：2004-04-13
申请号：US10172376
申请日：2002-06-14
申请人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
发明人： Pierangelo Confalonieri , Marco Zamprogno , Francesca Girardi
IPC分类号： H03M112
CPC分类号： H03M1/181 , H03M1/468
摘要： A method of operating an SAR-type analog-to-digital converter to match the dynamic range of an input voltage signal to be converted with the full scale range of the converter, the converter including at least one array of binary weighted capacitors. The method includes the step of obtaining a digital gain code that represents the ratio between the full scale range and the dynamic range of the voltage signal to be converted, applying the voltage signal to be converted to the capacitor array so as to charge with the voltage signal to be converted only those array capacitors having the same binary weights as the bits of the gain code that have a selected binary value, and selectively coupling the capacitors of the array to one of a first and second predetermined reference voltage terminals according to an SAR technique, to obtain an output digital code corresponding to the input voltage signal.
摘要翻译：一种操作SAR型模数转换器以匹配要转换的输入电压信号的动态范围与转换器的满量程范围的方法，所述转换器包括至少一个二进制加权电容器阵列。该方法包括获得数字增益代码的步骤，该数字增益代码表示满量程范围和要转换的电压信号的动态范围之间的比率，将要转换的电压信号施加到电容器阵列，以便对电压进行充电信号仅转换具有与具有选定二进制值的增益码的位相同的二进制权重的阵列电容器，并且根据SAR选择性地将阵列的电容器耦合到第一和第二预定参考电压端子之一技术，以获得对应于输入电压信号的输出数字代码。

56. 发明授权

US06600437B1 High resolution, high speed, low power switched capacitor digital to analog converter 有权
标题翻译：高分辨率，高速度，低功耗开关电容数字到模拟转换器
公开(公告)号：US06600437B1
公开(公告)日：2003-07-29
申请号：US10115272
申请日：2002-04-01
申请人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
发明人： Pierangelo Confalonieri , Marco Zamprogno , Angelo Nagari
IPC分类号： H03M166
CPC分类号： H03M1/68 , H03M1/468 , H03M1/804
摘要： A switched capacitor digital to analog converter includes first and second converter segments having respective first and second arrays of binary weighted capacitors. Each capacitor of the first segment has a first electrode connected to a first common node and a second electrode connected through respective switches to one of first and second reference voltage terminals. Each capacitor of the second segment has a first electrode connected to a second common node and a second electrode connected through respective switches to one of the first and second reference voltage terminals. The converter includes a coupling capacitor connected between the first and second common nodes and capacitance means connected between the first common node and a reference voltage terminal. The coupling capacitor and capacitance means have capacitances, Cs and CATT respectively, that substantially satisfy the relationship: (2p−1)·Cs−CATT=2p·C, where p is the number of bits coded in the first converter segment and C is the unit capacitance.
摘要翻译：开关电容器数模转换器包括具有相应的第二和第二二进制加权电容器阵列的第一和第二转换器段。第一段的每个电容器具有连接到第一公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。第二段的每个电容器具有连接到第二公共节点的第一电极和通过各个开关连接到第一和第二参考电压端子之一的第二电极。该转换器包括连接在第一和第二公共节点之间的耦合电容器和连接在第一公共节点和参考电压端子之间的电容装置。耦合电容器和电容装置分别具有电容Cs和CATT，其基本上满足以下关系：（2p-1）.C-CATT = 2p.C，其中p是在第一转换器段中编码的位数，C是单位电容。

57. 发明授权

US5712777A Voltage multiplier with linearly stabilized output voltage 失效
标题翻译：具有线性稳定输出电压的电压倍增器
公开(公告)号：US5712777A
公开(公告)日：1998-01-27
申请号：US414277
申请日：1995-03-31
申请人： Germano Nicollini , Pierangelo Confalonieri
发明人： Germano Nicollini , Pierangelo Confalonieri
IPC分类号： H01L27/04 , H01L21/822 , H02M3/07
CPC分类号： H02M3/07 , H02M2001/0045
摘要： A voltage multiplier includes a first charge transfer capacitor designed to take and transfer electrical charges from the input terminal to the output terminal, a second capacitor for charge storage connected between the output terminal and ground and an output voltage stabilization circuit. The output voltage stabilization circuit includes an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage and the output voltage of the voltage multiplier. The continuous voltage is applied to one terminal of said charge transfer capacitor so that the potential at the other terminal of the capacitor changes proportionally to the output voltage of the voltage multiplier.
摘要翻译：电压倍增器包括：第一电荷转移电容器，被设计用于从输入端子到输出端子接收和传送电荷;第二电容器，用于连接在输出端子和地之间的电荷存储器;以及输出电压稳定电路。输出电压稳定电路包括积分器，其被设计为产生对应于参考电压和电压倍增器的输出电压之间的差的连续电压。将连续电压施加到所述电荷转移电容器的一个端子，使得电容器另一端的电位与电压倍增器的输出电压成比例地变化。

58. 发明授权

US5606625A Digital circuit to regulate the gain of an amplifier stage 失效
标题翻译：数字电路来调节放大器级的增益
公开(公告)号：US5606625A
公开(公告)日：1997-02-25
申请号：US249316
申请日：1994-05-26
申请人： Carlo Dallavalle , Carlo Crippa , Pierangelo Confalonieri
发明人： Carlo Dallavalle , Carlo Crippa , Pierangelo Confalonieri
IPC分类号： H03G3/20 , H03G3/30 , H03G5/16 , H03G3/00
CPC分类号： H03G3/3089
摘要： A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.
摘要翻译：提供了一种用于控制编码信号接收通道的放大器级的增益的数字电路。电路包括通过编码信号整流电路和增益控制级耦合到接收信道的输入端的峰值检测器。增益控制级包括数字比较器，其具有分别连接到峰值检测器的输出端子和存储器的两个输入端子，以及耦合到放大器级的增益控制端子的输出端子。存储器的地址可选择内容包含编码形式的预定峰值。

59. 发明授权

US5552747A Driver circuit compatible with low supply voltages 失效
标题翻译：驱动电路兼容低电源电压
公开(公告)号：US5552747A
公开(公告)日：1996-09-03
申请号：US457759
申请日：1995-06-01
申请人： Luciano Tomasini , Rinaldo Castello , Pierangelo Confalonieri
发明人： Luciano Tomasini , Rinaldo Castello , Pierangelo Confalonieri
IPC分类号： H03K17/06 , H03K17/687 , G05F1/10 , G05F3/02
CPC分类号： H03K17/063
摘要： A driver circuit, for an electronic switch which is to be operated from a clock signal, comprises an inverter driven by the clock signal, and a voltage doubler which is connected to supply the inverter and connected to be driven by the complementary clock signal.
摘要翻译：用于从时钟信号操作的电子开关的驱动电路包括由时钟信号驱动的反相器，以及连接以提供反相器并连接以由互补时钟信号驱动的倍压器。

60. 发明授权

US5349244A Initialization circuit for memory registers 失效
标题翻译：存储器寄存器的初始化电路
公开(公告)号：US5349244A
公开(公告)日：1994-09-20
申请号：US982288
申请日：1992-11-25
申请人： Pierangelo Confalonieri
发明人： Pierangelo Confalonieri
IPC分类号： G06F12/16 , G06F1/24 , G11C7/20 , G11C7/22 , H03K3/356 , H03K17/22 , H03K3/01
CPC分类号： H03K3/356008 , G11C7/20 , G11C7/22 , H03K17/223
摘要： An initialization circuit, particularly for memory registers, being of a type which comprises a signal input to which a supply voltage is applied, and an initialization output at which a voltage signal is produced which is equal to the supply voltage up to a predetermined tripping value for the circuit, further comprises a second output connected to the register and being also an initialization output driven to a null voltage value upon the supply voltage dropping below the tripping value.
摘要翻译：特别是用于存储器寄存器的初始化电路是包括施加电源电压的信号输入的类型，以及产生电压信号的初始化输出，该电压信号等于高达预定跳闸值的电源电压对于电路，还包括连接到寄存器的第二输出端，并且还是当电源电压下降到跳闸值以下时被驱动为零电压值的初始化输出。

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