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    • 51. 发明授权
    • Programmable logic device with logic block outputs coupled to adjacent
logic block output multiplexers
    • 具有耦合到相邻逻辑块输出多路复用器的逻辑块输出的可编程逻辑器件
    • US5483178A
    • 1996-01-09
    • US207012
    • 1994-03-04
    • John C. CostelloRakesh H. Patel
    • John C. CostelloRakesh H. Patel
    • H03K19/173H03K19/177
    • H03K19/1737
    • A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.
    • 提供了一种可编程逻辑器件,其包含以行和列排列的多个逻辑阵列块。 逻辑阵列块与每行中的水平导体和每列中的垂直导体互连。 逻辑阵列块和导体之间的互连使用可编程逻辑进行配置。 一些可编程逻辑用于将逻辑阵列块输入端子选择性地连接到水平导体。 每列中的附加逻辑用于选择性地将水平导体连接到来自相邻列的相同列或逻辑阵列块输出端子的逻辑阵列块输出端子。 附加逻辑防止某些互连通路被阻塞,并增加可编程逻辑器件的互连方案的总体灵活性,从而提高器件性能。
    • 60. 发明授权
    • Apparatus and method for margin testing single polysilicon EEPROM cells
    • 单个多晶硅EEPROM单元的边缘测试的装置和方法
    • US06781883B1
    • 2004-08-24
    • US10620917
    • 2003-07-15
    • Raminda U. MaduraweMyron W. WongJohn C. CostelloJames D. SansburyBruce E. Mielk
    • Raminda U. MaduraweMyron W. WongJohn C. CostelloJames D. SansburyBruce E. Mielk
    • G11C1606
    • H01L27/11521G11C16/04G11C16/0441G11C16/26G11C16/3427G11C29/50G11C29/50004G11C2216/10H01L27/115H01L27/11558
    • Disclosed is a method and apparatus for evaluating margin voltages in single poly EEPROM cells. Briefly, the invention involves shifting the cell's threshold voltage higher, resulting in a corresponding rise in the margin voltage, so that testing for the erase margin may be conducted in the positive voltage range. The present invention implements a variety of solutions to the problem, including both innovations in cell processing and circuitry. In one embodiment, the process steps employed to create the floating gate transistor are changed in order to increase its threshold voltage. Alternatively, or in combination with these general process changes, the width of the floating gate transistor may be reduced, resulting in a corresponding increase in the margin voltage. Circuit modifications include providing a separate test mode condition where the sense amp trip current is higher than under normal operation, and raising the source line's voltage level with a new sense amp optimization, or only during the margin testing mode, both of which shift the erase margin voltages for the cell into the testable range.
    • 公开了一种用于评估单个多层EEPROM单元中的边缘电压的方法和装置。 简而言之,本发明涉及将电池的阈值电压更高,导致余量电压的相应上升,从而可以在正电压范围内进行擦除裕度的测试。 本发明实现了针对该问题的各种解决方案,包括在小区处理和电路中的创新。 在一个实施例中,用于产生浮栅晶体管的工艺步骤被改变以增加其阈值电压。 或者,或者与这些一般的工艺变化相结合,浮栅晶体管的宽度可能会减小,导致余量电压的相应增加。 电路修改包括提供单独的测试模式条件,其中感测放大器跳闸电流高于正常操作,并且通过新的感测放大器优化提高源极线路的电压电平,或者仅在裕度测试模式期间,两者都移动擦除 电池的裕度电压进入可测量范围。