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51. 发明授权

US4105335A Interferometric optical phase discrimination apparatus 失效
标题翻译：干涉光学相位鉴别装置
公开(公告)号：US4105335A
公开(公告)日：1978-08-08
申请号：US813298
申请日：1977-07-06
申请人： Nobuyoshi Tanaka , Naoki Ayata , Mitsuo Takeda , Susumu Matsumura , Kazuya Matsumoto
发明人： Nobuyoshi Tanaka , Naoki Ayata , Mitsuo Takeda , Susumu Matsumura , Kazuya Matsumoto
IPC分类号： G01B9/02 , G01B11/06 , G02B21/06
CPC分类号： G01B9/0209 , G01B11/06 , G01B11/0675
摘要： Film of a known refractive index whose thickness is to be measured is illuminated by a white light beam. Two wave fronts from both sides of the film are directed to an interferometer. The wave fronts are out of phase in accordance with the thickness of the film. The two wave fronts are amplitude-split, respectively, by the beam splitter of the interferometer. Two of the split wave fronts are tilted by tilting means in the interferometer. The other two split wave fronts, as well as the two tilted wave fronts, are directed to an interference surface. Thus, there is formed a white interference pattern on the interference surface. The white interference pattern has a middle peak and two side peaks. The space interval between these peaks is measured by a scanner. By knowing the peak-to-peak interval, it is possible to discriminate the space interval between both sides of the film.
摘要翻译：其厚度被测量的已知折射率的膜被白光束照射。电影两侧的两个波前被引导到干涉仪。根据薄膜的厚度，波前是相位相异的。两个波前分别由干涉仪的分束器进行振幅分割。两个分波锋面通过倾斜装置在干涉仪中倾斜。另外两个分裂波阵面以及两个倾斜的波前方向被引导到干涉面。因此，在干涉面上形成白色干涉图案。白色干涉图案具有中间峰和两个边峰。这些峰之间的间隔由扫描仪测量。通过知道峰到峰间隔，可以区分膜的两侧之间的间隔。

52. 发明授权

US09372887B2 Compression ratio improvement by lazy match evaluation on the string search CAM 有权
标题翻译：压缩比改进通过懒惰匹配评估对字符串搜索CAM
公开(公告)号：US09372887B2
公开(公告)日：2016-06-21
申请号：US13977005
申请日：2011-11-01
申请人： Hiroshi Doji , Nishino Kiyoshi , Nobuyoshi Tanaka
发明人： Hiroshi Doji , Nishino Kiyoshi , Nobuyoshi Tanaka
IPC分类号： G06F17/30 , G06Q30/02 , G11C15/00 , H03M7/30 , G11C15/04
CPC分类号： G11C11/418 , G06F17/30286 , G06F17/30424 , G06F17/30595 , G06F17/30864 , G06F17/30867 , G06Q30/02 , G11C11/419 , G11C15/00 , G11C15/04 , H03M7/3086
摘要： A plurality of stored data sequences that match one or more search data sequences are determined. Each of the stored data sequences of the plurality of stored data sequences comprise a plurality of data elements and the stored data sequences are stored in a content addressable memory array. A longest stored data sequence of the plurality of stored data sequences is determined using a plurality of tracing circuits. An address associated with the longest stored data sequence of the plurality of stored data sequences is determined. A count of data elements of the longest stored data sequence of the plurality of stored data sequences is determined.
摘要翻译：确定与一个或多个搜索数据序列匹配的多个存储的数据序列。多个存储的数据序列的每个存储的数据序列包括多个数据元素，并且将存储的数据序列存储在内容可寻址存储器阵列中。使用多个跟踪电路确定多个存储的数据序列中存储的最长的数据序列。确定与多个存储的数据序列中最长存储的数据序列相关联的地址。确定多个存储的数据序列中最长存储的数据序列的数据元素的计数。

53. 发明申请

US20130159811A1 Method of Hybrid Compression Acceleration Utilizing Special and General Purpose Processors 有权
标题翻译：利用特殊通用处理器的混合压缩加速方法
公开(公告)号：US20130159811A1
公开(公告)日：2013-06-20
申请号：US13327111
申请日：2011-12-15
申请人： Giora Biran , Amit Golander , Kiyoshi Nishino , Nobuyoshi Tanaka
发明人： Giora Biran , Amit Golander , Kiyoshi Nishino , Nobuyoshi Tanaka
IPC分类号： H03M13/09
CPC分类号： H03M7/30 , H03M7/3086 , H03M13/09 , H03M13/6312
摘要： A novel and useful hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.
摘要翻译：一种新颖有用的混合机制，其硬件加速与软件相结合，使得实现的压缩率显着增加，同时保持原始压缩比（例如，使用完全DHT而不是SHT或近似）。压缩加速机制适用于与通用处理器紧密耦合的硬件加速器。压缩任务在硬件和软件之间进行分割和并行化，其中每个压缩任务分为两个加速请求：使用硬件加速执行SHT编码并提供后LZ频率统计的第一请求; 以及使用在软件中生成的DHT来执行SHT解码和DHT编码的第二请求。

54. 发明申请

US20120139763A1 DECODING ENCODED DATA 失效
标题翻译：解码编码数据
公开(公告)号：US20120139763A1
公开(公告)日：2012-06-07
申请号：US13313772
申请日：2011-12-07
申请人： Kiyoshi Takemura , Nobuyoshi Tanaka , Makoto Ogawa , Tadayuki Okada
发明人： Kiyoshi Takemura , Nobuyoshi Tanaka , Makoto Ogawa , Tadayuki Okada
IPC分类号： H03M5/00
CPC分类号： H03M7/4031 , G06T9/005 , H03M7/30 , H03M7/40 , H03M7/46
摘要： A method for decoding encoded data. The method includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.
摘要翻译：一种解码编码数据的方法。该方法包括接收通过用位串替换多个字符中的每一个而编码的数据。该方法还包括基于定义信息记录与每个比特长度相对应的字符中的至少一个，并且基于字符数生成解码信息，其中解码信息包括用于分类的比特串信息位串以与位长度相关联的预定顺序的位长度顺序排列。该方法还包括响应于接收到特定比特长度，通过将对应于特定比特长度的字符插入与阵列中的特定比特长度相对应的位置来生成字符以比特长度顺序排序的字符信息其中至少一个位长度。

55. 发明授权

US07581564B2 Protector 失效
标题翻译：保护者
公开(公告)号：US07581564B2
公开(公告)日：2009-09-01
申请号：US12116376
申请日：2008-05-07
申请人： Nobuyoshi Tanaka , Masato Ibaraki , Tsutomu Sakata , Toshitsugu Morii
发明人： Nobuyoshi Tanaka , Masato Ibaraki , Tsutomu Sakata , Toshitsugu Morii
IPC分类号： F16L21/00
CPC分类号： F16L25/0045 , F16L21/06 , F16L41/021 , F16L47/32 , F16L57/00 , Y10S285/903 , Y10S285/921
摘要： A protector (10) has two half members (20, 40) forming a tubular shape upon being assembled. One half member (20) includes a pair of temporary fixing ribs (26A, 26B) projecting more than a contact edge (23) with the other half member (40) and standing up at the opposite sides of each of corrugated tubes (80A, 80B), each pair of temporary fixing ribs (26A, 26B) are shaped to be insertable into grooves (81A, 81B) of the corresponding corrugated tube (80A, 80B), and stand-up ends (27A, 27B) of the pair of temporary fixing ribs (26A, 26B) are bent to approach each other along the groove (81A, 81B) of the corrugated tube (80A, 80B).
摘要翻译：保护器（10）在组装时具有形成管状形状的两个半部件（20,40）。一个半构件（20）包括一对临时固定肋（26A，26B），该对临时固定肋（26A，26B）比另一个半构件（40）的接触边缘（23）多突出，并且在每个波纹管（80A， 80B），每对临时固定肋（26A，26B）成形为可插入到相应的波纹管（80A，80B）的凹槽（81A，81B）中，并且该对的立起端（27A，27B）临时固定肋（26A，26B）沿着波纹管（80A，80B）的凹槽（81A，81B）彼此弯曲。

56. 发明申请

US20090187793A1 EFFECTIVE METHOD TO PERFORM MEMORY TEST USING MULTIPLE PROCESSOR UNIT, DMA, AND SIMD INSTRUCTION 失效
标题翻译：使用多个处理器单元，DMA和SIMD指令执行存储器测试的有效方法
公开(公告)号：US20090187793A1
公开(公告)日：2009-07-23
申请号：US12357080
申请日：2009-01-21
申请人： Hiroshi Dohji , Hironori Makimura , Minoru Kida , Nobuyoshi Tanaka
发明人： Hiroshi Dohji , Hironori Makimura , Minoru Kida , Nobuyoshi Tanaka
IPC分类号： G06F11/26 , G06F13/28
CPC分类号： G11C29/56 , G11C2029/0401 , G11C2029/2602
摘要： To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS). The method and the like including: MP allocating a partial memory region (PMA) in MM to each SP; MP requesting each SP to test the allocated PMA; each SP filling LS thereof with initial data in response to receiving the request; each SP transferring the data stored in LS thereof to PMA by using a DMA transfer; each SP transferring the data stored in PMA to LS thereof by a DMA transfer; and SP testing the data in LS; and MP judging a test result on MM by putting together the tests results in response to the completion of all the tests by respective SP.
摘要翻译：提供一种用于测试多处理器系统中的主存储器的方法等，与单处理器用于测试的情况相比，其能够减少测试执行时间并相应地减少启动时间。本发明提供了一种用于在包括主处理器（MP）和多个子处理器（SP）的多处理器系统（MPS）中测试主存储器（MM）的方法，每个子处理器具有DMA传输机制和本地存储器（LS）。所述方法等包括：MP向每个SP分配MM中的部分存储区域（PMA）; MP要求每个SP测试分配的PMA; 每个SP响应于接收到请求而填充其初始数据; 每个SP通过使用DMA传输将其LS中存储的数据传送到PMA; 每个SP通过DMA传输将存储在PMA中的数据传送到LS; 并对LS中的数据进行SP测试; 并且MP通过将测试结果组合在一起来响应于相应SP的所有测试的完成来判断MM的测试结果。

57. 发明授权

US07407403B2 Connector 失效
标题翻译：连接器
公开(公告)号：US07407403B2
公开(公告)日：2008-08-05
申请号：US11338010
申请日：2006-01-24
申请人： Nobuyoshi Tanaka , Yoji Kanaoka , Takayuki Nakatsugawa
发明人： Nobuyoshi Tanaka , Yoji Kanaoka , Takayuki Nakatsugawa
IPC分类号： H01R13/627
CPC分类号： H01R13/6272
摘要： A male housing (1) has a hood (5) for receiving a female housing (2) and the female housing (2) has a locking arm (9) for engaging the hood (5) when the housings (1, 2) are fit together. Protection walls (19) are formed on the female housing (2) on opposite sides of the locking arm (9). The protection walls (19) are substantially flush with the hood (5) when the housings (1, 2) are fit together. An operation portion (20) of the locking arm (9) also is substantially flush with the hood (5) when the housings (1, 2) are fit together. A predetermined interval is set between opposed ends of the protection wall (19) and the hood (5) and between the operation portion (20) and the hood (5). Thus, an operator's gloves will not be caught while fitting the male and female housing (1, 2) together.
摘要翻译：阳壳体（1）具有用于容纳阴壳体（2）的罩（5），并且阴壳体（2）具有当壳体（1,2）为适合在一起。保护壁（19）形成在锁定臂（9）的相对侧上的阴壳体（2）上。当壳体（1,2）装配在一起时，保护壁（19）基本上与罩（5）齐平。当壳体（1,2）装配在一起时，锁定臂（9）的操作部分（20）也基本上与罩（5）齐平。在保护壁（19）和罩（5）的相对端之间以及操作部（20）和罩（5）之间设置预定间隔。因此，在将男女外壳（1,2）安装在一起时，操作者的手套不会被抓住。

58. 发明授权

US07275313B2 Unlocking jig 有权
标题翻译：解锁夹具
公开(公告)号：US07275313B2
公开(公告)日：2007-10-02
申请号：US10747414
申请日：2003-12-29
申请人： Kiyofumi Ichida , Nobuyoshi Tanaka
发明人： Kiyofumi Ichida , Nobuyoshi Tanaka
IPC分类号： B23P19/00
CPC分类号： H01R43/22 , H01R13/4367 , H01R13/633 , Y10T29/53209 , Y10T29/53213 , Y10T29/53222 , Y10T29/53239
摘要： An unlocking jig (40) is fit on a female housing (10) from below. As a result, a guide groove (43A) on a bottom portion (43) of the unlocking jig (40) engages a convexity (22C) on a lower surface of the female housing (10) and a guide groove (43B) on an arm (45) engages a convexity (22B) on a side surface of the female housing (10). The unlocking jig (40) has unlocking claws (a1, a2) that engage short locking pieces (38B, 38C) when the unlocking jig (40) is moved and unlock the short locking pieces (38B, 38C) from locks (22B, 22C) on the housing (10).
摘要翻译：解锁夹具（40）从下方装配在阴壳体（10）上。结果，解锁夹具（40）的底部（43）上的引导槽（43A）与阴壳体（10）的下表面上的凸起（22C）和引导槽（43B）接合）与凸缘（22B）接合在阴壳体（10）的侧表面上。当解锁夹具（40）移动并解锁短锁定件（38B，38C）时，解锁夹具（40）具有接合短锁定件（38B，38C）的解锁爪（a 1，a 2）来自壳体（10）上的锁（22B，22C）。

59. 发明申请

US20070197059A1 Connector for use in substrate 有权
标题翻译：用于基板的连接器
公开(公告)号：US20070197059A1
公开(公告)日：2007-08-23
申请号：US11656719
申请日：2007-01-23
申请人： Nobuyoshi Tanaka
发明人： Nobuyoshi Tanaka
IPC分类号： H01R12/00
CPC分类号： H01R12/7017 , H01R12/724
摘要： A fixing part (12) has two resiliently deformable legs (18) separated by a slot (17). A locking projection (19) is formed at a distal end (19C) of the fixing part (12) and has a locking surface (19A) spaced from the distal end (19C). A maximum cross-sectional dimension (A) of the fixing part (12) at the locking surface (19A) exceeds the diameter (d) of a through-hole (71) in a substrate (70). A tapered sliding-contact surface (19B) extends from the locking surface (19A) to the distal end (19C). Noncontact surfaces (21) are at opposite circumferential ends of each sliding contact surface (19B) and substantially adjacent the slot (17). The noncontact surfaces (22) of each locking projection (19) are spaced from one another at the slot (17) by distances that are no greater than the diameter (d) of the through-hole (71).
摘要翻译：固定部分（12）具有由槽（17）分开的两个可弹性变形的支脚（18）。锁定突起（19）形成在固定部分（12）的远端（19C）处并且具有与远端（19C）间隔开的锁定表面（19A）。固定部分（12）在锁定表面（11A）处的最大横截面尺寸（A）超过衬底（70）中的通孔（71）的直径（d）。锥形滑动接触表面（19B）从锁定表面（19A）延伸到远端（19C）。非接触表面（21）在每个滑动接触表面（19B）的相对的周向端部处并且基本上邻近狭槽（17）。每个锁定突起（19）的非接触表面（22）在槽（17）处彼此间隔开不超过通孔（71）的直径（d）的距离。

60. 发明授权

US07035994B2 Storage device, information processing system having storage device, format method for storage device, data recording method, and program for implementing formatting and data recording 失效
标题翻译：存储装置，具有存储装置的信息处理系统，存储装置的格式化方法，数据记录方法以及用于实现格式化和数据记录的程序
公开(公告)号：US07035994B2
公开(公告)日：2006-04-25
申请号：US10454141
申请日：2003-06-03
申请人： Nobuyoshi Tanaka , Kiyoshi Nishino , Akihiro Ogura
发明人： Nobuyoshi Tanaka , Kiyoshi Nishino , Akihiro Ogura
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0689 , G06F12/0866 , G11B20/1217
摘要： To provide a storage device capable of shortening a formatting time and a data recording time, and an information processing system, method and program. The storage device of the invention has at least one storage medium 40, storing means 32 for storing plural patterns of format data for each pattern, receiving means 34 for receiving a sector address specifying a sector of the storage medium 40 to be written and a pattern identifier specifying a pattern of the format data to be written, and writing means 36 for reading the format data having the pattern corresponding to the pattern identifier from the storing means 32 and writing the read format data into the sector of the storage medium 40 corresponding to the received sector address.
摘要翻译：提供能够缩短格式化时间和数据记录时间的存储装置，以及信息处理系统，方法和程序。本发明的存储装置具有至少一个存储介质40，存储装置32，用于存储每种模式的格式数据的多种格式;接收装置34，用于接收指定要写入的存储介质40的扇区的扇区地址和模式指定要写入的格式数据的模式的标识符;以及写入装置36，用于从存储装置32读取具有对应于模式标识符的模式的格式数据，并将读取的格式数据写入对应于接收的扇区地址。

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