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51. 发明授权

US07273806B2 Forming of high aspect ratio conductive structure using injection molded solder 有权
标题翻译：使用注塑焊料形成高纵横比导电结构
公开(公告)号：US07273806B2
公开(公告)日：2007-09-25
申请号：US10905013
申请日：2004-12-09
申请人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： Robert A. Groves , Peter A. Gruber , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L21/44
CPC分类号： H05K3/3468 , G01R1/07314 , G01R3/00 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/19041 , H01L2924/19042 , H05K3/325 , H05K2201/09745 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K2203/162 , H05K2203/167 , H01L2224/0401
摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
摘要翻译：公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。导电结构包括通过注射成型的焊料形成的高纵横比结构。本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。此外，该方法可以向后兼容并可定制。

52. 发明授权

US06825075B2 Method of fabricating MIM capacitor with the encapsulated metal structure serving as the lower plate 失效
标题翻译：制造具有封装金属结构的MIM电容器作为下板的方法
公开(公告)号：US06825075B2
公开(公告)日：2004-11-30
申请号：US10757214
申请日：2004-01-14
申请人： Kevin S. Petrarca , Donald Canaperi , Mahadevaiyer Krishnan , Kenneth Jay Stein , Richard P. Volant
发明人： Kevin S. Petrarca , Donald Canaperi , Mahadevaiyer Krishnan , Kenneth Jay Stein , Richard P. Volant
IPC分类号： H01L218242
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/7684 , H01L28/60
摘要： A method is described for fabricating an encapsulated metal structure in a feature formed in a substrate. The sidewalls and bottom of the feature are covered by a barrier layer and the feature is filled with metal, preferably by electroplating. A recess is formed in the metal, and an additional barrier layer is deposited, covering the top surface of the metal and contacting the first barrier layer. The additional barrier layer is planarized, preferably by chemical-mechanical polishing. The method may be used in fabricating a MIM capacitor, with the encapsulated metal structure serving as the lower plate of the capacitor. A second substrate layer is deposited on the top surface of the substrate, with an opening overlying the encapsulated metal structure. A dielectric layer is deposited in the opening, covering the encapsulated metal structure at the bottom thereof. An additional layer, serving as the upper plate of the capacitor, is deposited to cover the dielectric layer and to fill the opening. The dielectric layer and the additional layer are planarized, preferably by CMP.
摘要翻译：描述了一种在衬底中形成的特征中制造封装金属结构的方法。特征的侧壁和底部被阻挡层覆盖，并且该特征被金属填充，优选地通过电镀。在金属中形成凹部，并且沉积附加的阻挡层，覆盖金属的顶表面并与第一阻挡层接触。优选通过化学机械抛光将附加阻挡层平坦化。该方法可用于制造MIM电容器，其中封装的金属结构用作电容器的下板。第二衬底层沉积在衬底的顶表面上，具有覆盖封装的金属结构的开口。介电层沉积在开口中，覆盖其底部的封装金属结构。作为电容器的上板的附加层被沉积以覆盖电介质层并填充开口。介电层和附加层优选通过CMP平坦化。

53. 发明授权

US06613641B1 Production of metal insulator metal (MIM) structures using anodizing process 失效
公开(公告)号：US06613641B1
公开(公告)日：2003-09-02
申请号：US09764834
申请日：2001-01-17
申请人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
发明人： Richard P. Volant , John M. Cotte , Kevin S. Petrarca , Kenneth J. Stein
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/31687 , Y10S438/957
摘要： Metal-insulator-metal capacitor structures are formed in semiconductor substrates using an anodization procedure on deposited underlying metalization followed by deposition of the second metal and planarization by chemical-mechanical polishing or other procedures. The process is additive in character, as opposed to traditional subtractive etch processes for forming capacitor structures. In addition, the process can be used in damascene applications, and can be used to form a wide variety of capacitive structures while reducing the number of mask layers required for formation.

54. 发明授权

US06534863B2 Common ball-limiting metallurgy for I/O sites 有权
公开(公告)号：US06534863B2
公开(公告)日：2003-03-18
申请号：US09781121
申请日：2001-02-09
申请人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
发明人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

55. 发明授权

US06383893B1 Method of forming a crack stop structure and diffusion barrier in integrated circuits 有权
标题翻译：在集成电路中形成裂纹停止结构和扩散势垒的方法
公开(公告)号：US06383893B1
公开(公告)日：2002-05-07
申请号：US09752622
申请日：2000-12-28
申请人： Edward S. Begle , Richard P. Volant , Kevin S. Petrarca
发明人： Edward S. Begle , Richard P. Volant , Kevin S. Petrarca
IPC分类号： H01L2146
CPC分类号： H01L23/585 , H01L2924/0002 , Y10S438/94 , H01L2924/00
摘要： A method for forming a crack stop structure and a barrier to the diffusion of oxygen and water vapor in integrated circuits is provided.
摘要翻译：提供了一种形成裂纹停止结构的方法以及集成电路中氧气和水蒸气扩散的障碍。

56. 发明授权

US06344125B1 Pattern-sensitive electrolytic metal plating 失效
标题翻译：图案感应电解金属电镀
公开(公告)号：US06344125B1
公开(公告)日：2002-02-05
申请号：US09544053
申请日：2000-04-06
申请人： Peter S. Locke , Kevin S. Petrarca , Seshadri Subbanna , Richard P. Volant
发明人： Peter S. Locke , Kevin S. Petrarca , Seshadri Subbanna , Richard P. Volant
IPC分类号： C25D502
CPC分类号： C25D7/123 , H01L21/2885 , H01L21/32051
摘要： A process for the electrolytic deposition of a metal, preferably copper or an alloy of copper, directly onto a barrier layer coated on a dielectric layer. The process is advantageous because it electrolytically deposits metal in a pattern that is either the duplicate of a first conductive pattern under the dielectric or the inverse image of the first conductive pattern, depending on the first conductive pattern shape. Thus, metal is deposited on the barrier layer duplicating a first conductive pattern under the dielectric layer when the first pattern is a serpentine pattern and the metal deposits in the spaces between the conductive lines of a first conductive pattern of a discrete passive element such as a spiral.
摘要翻译：一种用于将金属，优选铜或铜合金电解沉积到涂覆在电介质层上的阻挡层上的方法。该方法是有利的，因为它取决于第一导电图案形状，电解沉积在第一导电图案的电介质下的第一导电图案的副本或第一导电图案的逆图像的图案中的金属。因此，当第一图案是蛇形图案时，金属沉积在阻挡层上，复制第一导电图案下方的第一导电图案，并且金属沉积在离散无源元件的第一导电图案的导线之间的空间中，例如螺旋。

57. 发明授权

US06339024B1 Reinforced integrated circuits 失效
标题翻译：强化集成电路
公开(公告)号：US06339024B1
公开(公告)日：2002-01-15
申请号：US09605728
申请日：2000-06-28
申请人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
发明人： Kevin S. Petrarca , John E. Heidenreich, III , Judith M. Rubino , Carlos J. Sambucetti , Richard P. Volant , George F. Walker
IPC分类号： H01L2044
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/13022 , H01L2224/13099 , H01L2924/0001 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14
摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.
摘要翻译：一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

58. 发明申请

US20100047990A1 METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR 有权
标题翻译：制造高Q因子集成电路电感的方法
公开(公告)号：US20100047990A1
公开(公告)日：2010-02-25
申请号：US12612743
申请日：2009-11-05
申请人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
发明人： Daniel C. Edelstein , Panayotis C. Andricacos , John M. Cotte , Hariklia Deligianni , John H. Magerlein , Kevin S. Petrarca , Kenneth J. Stein , Richard P. Volant
IPC分类号： H01L21/02
CPC分类号： H01L24/12 , H01L23/5227 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L27/08 , H01L28/10 , H01L2224/0401 , H01L2224/04042 , H01L2224/05007 , H01L2224/05014 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05084 , H01L2224/05555 , H01L2224/05557 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48744 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19042 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.
摘要翻译：一种形成电感器的方法。该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; （d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

59. 发明授权

US06815813B1 Self-contained heat sink and a method for fabricating same 失效
标题翻译：独立散热片及其制造方法
公开(公告)号：US06815813B1
公开(公告)日：2004-11-09
申请号：US10604211
申请日：2003-07-01
申请人： Timothy J. Dalton , Kevin S. Petrarca , Michelle L. Steen , Cornelia K. Tsang , Richard P. Volant
发明人： Timothy J. Dalton , Kevin S. Petrarca , Michelle L. Steen , Cornelia K. Tsang , Richard P. Volant
IPC分类号： H01L2334
CPC分类号： H01L23/58 , H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： A system and method are provided for thermal dissipation from a heat producing electronic device. The system includes a substrate for fabricating integrated circuits, the substrate having a first face and a second face. The second face is disposed substantially parallel to the first face having an electronic device disposed therein. A metallized crack stop is disposed in the first face surrounding the electronic device. A plurality of first metal conduits extend through the substrate from the second face thereof to the crack stop, wherein each first metal conduit is in thermal contact with the crack stop to provide a thermal drain from the electronic device to the second face.
摘要翻译：提供了一种从制热电子设备散热的系统和方法。该系统包括用于制造集成电路的基板，该基板具有第一面和第二面。第二面基本上平行于第一面设置，其中设置有电子装置。在电子设备周围的第一面设有金属化的裂纹停止件。多个第一金属导管从其第二面延伸穿过基板到裂缝停止部，其中每个第一金属导管与裂纹停止件热接触以提供从电子装置到第二面的热耗散。

60. 发明授权

US06798029B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06798029B2
公开(公告)日：2004-09-28
申请号：US10434999
申请日：2003-05-09
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2982
CPC分类号： H01H59/0009 , H01H2059/0018 , H01H2059/0072
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

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