专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08084692B2 Reducing noise coupling in high speed digital systems 有权
标题翻译：降低高速数字系统中的噪声耦合
公开(公告)号：US08084692B2
公开(公告)日：2011-12-27
申请号：US11924416
申请日：2007-10-25
申请人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
发明人： Moises Cases , Bradley D. Herrman , Kent B. Howieson , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham , Caleb J. Wesley
IPC分类号： H05K1/03
CPC分类号： H05K1/024 , H05K3/4611 , H05K3/4697 , H05K2201/09236 , H05K2201/09318 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T156/1013
摘要： An apparatus having reduced noise coupling includes a core layer having an upper and lower surface, the upper and lower surface each including a copper sheet layer, a pre-preg layer having an upper surface and a lower surface, the upper surface of the pre-preg layer coupled to the lower surface of the core layer, a core insulating layer having an upper surface and a lower surface, the upper surface of the core insulating layer coupled to the lower surface of the pre-preg layer, a return current reference layer disposed on the lower surface of the core insulator layer and high-speed signal traces disposed on the upper surface of the core insulating layer, each of the high speed signal traces disposed on a pedestal defined by a section of the pre-preg layer and the core insulating layer, each pedestal being separated by an air gap disposed between adjacent pedestals.
摘要翻译：具有降低的噪声耦合的装置包括具有上表面和下表面的芯层，所述上表面和下表面各自包括铜片层，具有上表面和下表面的预浸层，耦合到芯层的下表面的芯层绝缘层，具有上表面和下表面的芯绝缘层，芯绝缘层的上表面耦合到预浸层的下表面，返回电流参考层设置在芯绝缘体层的下表面和设置在芯绝缘层的上表面上的高速信号迹线，每个高速信号迹线设置在由预浸层的一部分限定的基座上，芯绝缘层，每个基座由设置在相邻基座之间的气隙分隔开。

52. 发明授权

US07987110B2 Managing organizational resources 失效
标题翻译：管理组织资源
公开(公告)号：US07987110B2
公开(公告)日：2011-07-26
申请号：US11828111
申请日：2007-07-25
申请人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
发明人： Moises Cases , Candice Leontine Coletrane , Bhyrav Murthy Mutnury , Scott Lee Winters
IPC分类号： G06Q10/00
CPC分类号： G06Q30/02 , G06Q10/06311 , G06Q10/06315 , G06Q50/01
摘要： A computer implemented method, apparatus, and computer program product for managing organizational resources. The process combines social group data with management information data to form social network data, wherein social group data is derived from interactions among a plurality of users of a social group. The process analyzes the social network data to identify associations among the plurality of users, and generates a multidimensional social network model using the associations among the plurality of users. Thereafter, the process presents a set of recommendations for allocation of the organizational resources, wherein the set of recommendations are derived from the social network model.
摘要翻译：一种用于管理组织资源的计算机实现的方法，装置和计算机程序产品。该过程将社会群体数据与管理信息数据组合以形成社交网络数据，其中社交群组数据源自社交群体的多个用户之间的交互。该过程分析社交网络数据以识别多个用户之间的关联，并且使用多个用户之间的关联来生成多维社交网络模型。此后，该过程提出了一组关于组织资源分配的建议，其中一组建议源于社交网络模型。

53. 发明授权

US07977574B2 Cable for high speed data communications 有权
标题翻译：电缆用于高速数据通信
公开(公告)号：US07977574B2
公开(公告)日：2011-07-12
申请号：US12265407
申请日：2008-11-05
申请人： Moises Cases , Daniel N. De Araujo , Bhyrav M. Mutnury , Bruce J. Wilkie
发明人： Moises Cases , Daniel N. De Araujo , Bhyrav M. Mutnury , Bruce J. Wilkie
IPC分类号： H01B7/00
CPC分类号： H01B13/26 , H01B11/1025 , Y10T29/49123
摘要： Cables and methods of manufacturing cables for high speed data communications, the cable including: a first inner conductor enclosed by a first dielectric layer and a second inner conductor enclosed by a second dielectric layer, the inner conductors and the dielectric layers parallel with and along a longitudinal axis; and folded conductive shield material wrapped in a rotational direction along and about the longitudinal axis around the inner conductors and the dielectric layers, including overlapped wraps along and about the longitudinal axis, the conductive shield material comprising a first conductive layer and second conductive layer separated by an inner-shield dielectric layer.
摘要翻译：用于制造用于高速数据通信的电缆的电缆和方法，所述电缆包括：被第一电介质层包围的第一内部导体和由第二电介质层包围的第二内部导体，所述内部导体和电介质层与纵轴; 以及折叠的导电屏蔽材料沿着并围绕纵向轴线围绕内部导体和电介质层缠绕，包括围绕纵向轴线重叠的包裹物，导电屏蔽材料包括由第一导电层和第二导电层分隔的第二导电层内屏蔽介电层。

54. 发明申请

US20110140709A1 LOCATING SHORT CIRCUITS IN PRINTED CIRCUIT BOARDS 有权
标题翻译：在印刷电路板中定位短路
公开(公告)号：US20110140709A1
公开(公告)日：2011-06-16
申请号：US12638044
申请日：2009-12-15
申请人： Moises Cases , Bhyrav M. Mutnury , Terence Rodrigues
发明人： Moises Cases , Bhyrav M. Mutnury , Terence Rodrigues
IPC分类号： G01R31/28 , G01R31/11
CPC分类号： G01R31/2812
摘要： One embodiment provides a method of locating a short circuit in a printed circuit board. Test signals may be injected at different test points on the circuit board. The distance between each test point and the short circuit may be determined according to how long it takes for a signal reflection at the short circuit to propagate back to each test point. The distances between the various test points and the short circuit can be used to narrow the possible locations of the short circuit or even to pinpoint the location of the short circuit.
摘要翻译：一个实施例提供了一种定位印刷电路板中的短路的方法。测试信号可以在电路板上的不同测试点注入。每个测试点和短路之间的距离可以根据短路信号反射传播回每个测试点所需的时间来确定。各种测试点和短路之间的距离可用于缩小短路的可能位置，甚至可以精确定位短路位置。

55. 发明申请

US20110103030A1 Packages and Methods for Mitigating Plating Stub Effects 审中-公开
标题翻译：减轻电镀桩影响的包装和方法
公开(公告)号：US20110103030A1
公开(公告)日：2011-05-05
申请号：US12610413
申请日：2009-11-02
申请人： Moises Cases , Tae Hong Kim , Bhyrav M. Mutnury , Nanju Na
发明人： Moises Cases , Tae Hong Kim , Bhyrav M. Mutnury , Nanju Na
IPC分类号： H01L23/52 , H01L21/60 , H05K7/00
CPC分类号： H01L23/647 , H01L23/49838 , H01L23/66 , H01L24/45 , H01L24/48 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19105 , H01L2924/3011 , H01L2924/00014
摘要： Packages and methods for mitigating plating stub effects. The semiconductor package includes an interposer substrate having a first side, a second side, a peripheral edge connecting the first side with the second side, a signal line on the first side, and an electrode pad on the first side. A semiconductor element is mounted on the first side of the interposer substrate. The semiconductor element is connected with the electrode pad by the signal line. A terminating resistor is mounted on the interposer substrate. A plating stub, which is located on the interposer substrate, has a first end portion that terminates near the peripheral edge of the interposer substrate and a second end portion that is electrically connected to the electrode. The first end portion is electrically connected through the terminating resistor to an electrical ground.
摘要翻译：用于减轻电镀桩效应的包装和方法。半导体封装包括具有第一侧，第二侧，连接第一侧与第二侧的周边边缘，第一侧上的信号线和第一侧上的电极焊盘的插入器基板。半导体元件安装在插入器基板的第一侧上。半导体元件通过信号线与电极焊盘连接。终端电阻器安装在插入器基板上。位于内插基板上的电镀短截线具有在中介基板的周缘附近终止的第一端部和与该电极电连接的第二端部。第一端部通过终端电阻器电连接到电接地。

56. 发明授权

US07868652B1 Off-die termination module with a spring loaded pin in a DIMM socket 有权
标题翻译：脱模终端模块，弹簧加载销插入DIMM插槽
公开(公告)号：US07868652B1
公开(公告)日：2011-01-11
申请号：US12632864
申请日：2009-12-08
申请人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： H03K17/16
CPC分类号： G06F13/4086
摘要： Off-die termination module for terminating memory module signal lines in a computer memory subsystem, the computer memory subsystem including a memory controller and a DIMM socket, the memory controller coupled to the DIMM socket via a memory module signal line, the off-die termination module including: an off-die termination component configured to terminate the memory module signal line upon activation; and a spring loaded notch pin implemented as part of the DIMM socket, the spring loaded notch pin configured to toggle activation of the off-die termination component in dependence upon presence of a DIMM in the DIMM socket including activating the off-die termination component upon removal of a DIMM from the DIMM socket and deactivating the off-die termination component upon installation of a DIMM in the DIMM socket.
摘要翻译：用于终止计算机存储器子系统中的存储器模块信号线的裸片终端模块，所述计算机存储器子系统包括存储器控制器和DIMM插槽，所述存储器控制器经由存储器模块信号线耦合到所述DIMM插槽，所述离线端子模块包括：非激活终端组件，被配置为在激活时终止所述存储器模块信号线; 以及作为所述DIMM插座的一部分实现的弹簧加载的凹口销，所述弹簧加载的凹口销被配置为根据DIMM插槽中存在的DIMM来切换所述离模端接部件的启动，包括在所述DIMM插座上激活所述离模终端组件从DIMM插槽中取出DIMM，并在DIMM插槽中安装DIMM时停用裸片端接组件。

57. 发明授权

US07813447B2 Apparatus, system, and method for dynamic phase equalization in a communication channel 有权
标题翻译：通信信道中动态相位均衡的装置，系统和方法
公开(公告)号：US07813447B2
公开(公告)日：2010-10-12
申请号：US11560257
申请日：2006-11-15
申请人： Daniel N. De Araujo , Moises Cases , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
发明人： Daniel N. De Araujo , Moises Cases , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin S. Patel , Nam H. Pham
IPC分类号： H04L25/03
CPC分类号： H04L25/0264 , H04L25/0286
摘要： An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.
摘要翻译：公开了用于通信信道中的动态相位均衡的装置，系统和方法。发射机历史模块从通过通信信道发送的数据流存储多个比特。发射机检测模块检测在数据流中前面的第一值的前转换比特的第一值的至少一个比特，然后跟随具有第二值的转换比特。驾驶员模块通过驱动通信信道来发送数据流。转换模块在预转换位的位时间间隔期间将通信通道预驱动到转换位的第二电压。

58. 发明授权

US07791227B2 Electromagnetic morphing apparatus for hot pluggable architected systems 失效
标题翻译：用于热插拔式架构系统的电磁变形装置
公开(公告)号：US07791227B2
公开(公告)日：2010-09-07
申请号：US11858663
申请日：2007-09-20
申请人： Moises Cases , Byron L. Krauter , Bhyrav M. Mutnury , Nam H. Pham
发明人： Moises Cases , Byron L. Krauter , Bhyrav M. Mutnury , Nam H. Pham
IPC分类号： H01B7/30
CPC分类号： H01P1/047 , H01R13/6464 , H05K1/0216 , H05K1/0231 , H05K1/0262 , H05K2201/093 , H05K2201/09309 , H05K2201/09663 , H05K2201/10189
摘要： In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity.
摘要翻译：在具有位于接地层和电压参考层之间的信号迹线的电子设备中，提供了用于以可减少由于寄生效应引起的信号劣化的方式将热可插拔设备连接到电子设备的系统和方法。第一设备具有连接器附近的第二参考层，其连接到跨连接器保持在给定电压电平的第二设备电压参考层。在连接器附近的第一器件中，信号迹线位于第一器件的接地层和由第二器件的电压调节器保持在给定电压之间的第二参考层之间。信号返回电流经过第二参考层行进到第一器件的第一参考层，该第一参考层由第一器件的电压调节器通过AC去耦电容器维持，使电流返回路径不连续性最小化。

59. 发明授权

US07730369B2 Method for performing memory diagnostics using a programmable diagnostic memory module 失效
标题翻译：使用可编程诊断存储器模块执行存储器诊断的方法
公开(公告)号：US07730369B2
公开(公告)日：2010-06-01
申请号：US11840498
申请日：2007-08-17
申请人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
发明人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
IPC分类号： G11C29/00
CPC分类号： G06F11/24
摘要： A method for performing memory diagnostics using a programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译：使用可编程诊断存储器模块执行存储器诊断的方法提供了存储器控制器和存储器子系统设计的增强的可测试性。可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。

60. 发明授权

US07725783B2 Method and apparatus for repeatable drive strength assessments of high speed memory DIMMs 有权
标题翻译：用于高速存储器DIMM的可重复驱动强度评估的方法和装置
公开(公告)号：US07725783B2
公开(公告)日：2010-05-25
申请号：US11780505
申请日：2007-07-20
申请人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
发明人： Moises Cases , Daniel N. de Araujo , Bradley D. Herrman , Erdem Matoglu , Bhyrav M. Mutnury , Pravin Patel , Nam H. Pham
IPC分类号： G11C29/00
CPC分类号： G01R31/2815 , G01R31/304 , G11C29/02 , G11C29/022 , G11C29/56 , G11C2029/5602
摘要： The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.
摘要翻译：本发明通过计算由诸如偶极天线的装置收集的辐射场的频率内容来评估存储器（DIMM）强度。辐射场由加速电荷产生，这是压摆率或DIMM强度的函数。辐射功率与驱动位的频率成正比。通过将辐射场与近场或存储场分离，DIMM强度内容与其他功能性DIMM问题（例如tRCD延迟，刷新周期，寻址模式等）隔离。通过检查辐射功率，现有技术的缺点，例如通过探测DIMM的触点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式