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51. 发明申请

US20120099048A1 LIGHT-EMITTING ELEMENT UNIT AND DISPLAY DEVICE 有权
标题翻译：发光元件单元和显示设备
公开(公告)号：US20120099048A1
公开(公告)日：2012-04-26
申请号：US13277417
申请日：2011-10-20
申请人： Shunpei YAMAZAKI , Yoshiharu Hirakata
发明人： Shunpei YAMAZAKI , Yoshiharu Hirakata
IPC分类号： G02F1/1335 , H01L33/58 , H01L33/08 , H01L33/50
CPC分类号： H01L33/505 , G02F1/133514 , G02F1/133603 , G02F1/133621 , H01L25/0753 , H01L33/465 , H01L33/486 , H01L33/50 , H01L33/54 , H01L33/56 , H01L33/62 , H01L2224/48227 , H01L2224/48465 , H01L2924/07811 , H01L2924/1461 , H01L2924/3025 , H01L2924/00
摘要： A light-emitting element unit which can improve color purity of light emitted from a color filter is provided. A display device with high color purity and high color reproducibility is provided. The light-emitting element unit includes a wiring board, a light-emitting element chip provided over the wiring board, a micro optical resonator provided over the wiring board and at the periphery of the light-emitting element chip, and a phosphor layer covering the light-emitting element chip and the micro optical resonator. The display device includes a display panel having a coloring layer and a backlight module having the light-emitting element unit. Examples of the display panel include: a liquid crystal panel; and a display panel including an opening portion provided over a first substrate, MEMS moving over the opening portion in the lateral direction, and a second substrate provided with a coloring layer in a portion corresponding to the opening portion.
摘要翻译：提供了可以提高从滤色器发出的光的色纯度的发光元件单元。提供了具有高纯度和高色彩再现性的显示装置。发光元件单元包括布线板，设置在布线板上的发光元件芯片，设置在布线板上和发光元件芯片周围的微光谐振器，以及覆盖该发光元件芯片的荧光体层发光元件芯片和微光谐振器。显示装置包括具有着色层的显示面板和具有发光元件单元的背光模块。显示面板的实例包括：液晶面板; 以及显示面板，包括设置在第一基板上的开口部分，在横向方向上在开口部分上移动的MEMS以及在与开口部分相对应的部分中设置有着色层的第二基板。

52. 发明申请

US20120074418A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120074418A1
公开(公告)日：2012-03-29
申请号：US13298469
申请日：2011-11-17
申请人： Shunpei YAMAZAKI
发明人： Shunpei YAMAZAKI
IPC分类号： H01L27/12
CPC分类号： H01L27/124 , H01L27/1214 , H01L27/127 , H01L29/42384 , H01L2029/7863
摘要： NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.
摘要翻译：本发明的NTFT在半导体层中具有沟道形成区域，n型第一，第二和第三杂质区域。第二杂质区域是与栅电极的锥形部分重叠的低浓度杂质区域，其间插入有栅极绝缘膜，并且第二杂质区域的杂质浓度从沟道形成区域逐渐增加到第一杂质区域。并且，第三杂质区域是不与栅电极重叠的低浓度杂质区域。此外，根据工作电压的差异，同一衬底上的多个NTFT分别具有不同的第二杂质区长度。也就是说，当第二TFT的工作电压高于第一TFT的工作电压时，第二TFT上的第二杂质区域的长度比第一TFT长。

53. 发明申请

US20120074407A1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20120074407A1
公开(公告)日：2012-03-29
申请号：US13021343
申请日：2011-02-04
申请人： Shunpei YAMAZAKI , Teruyuki FUJII , Ryota IMAHAYASHI , Shinya SASAGAWA , Motomu KURATA , Fumika TAGUCHI
发明人： Shunpei YAMAZAKI , Teruyuki FUJII , Ryota IMAHAYASHI , Shinya SASAGAWA , Motomu KURATA , Fumika TAGUCHI
IPC分类号： H01L27/06 , H01L21/336
CPC分类号： H01L27/0688 , G11C16/0416 , G11C16/0433 , G11C16/28 , H01L27/1052 , H01L27/11521 , H01L27/11551 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
摘要翻译：目的是提供一种具有新颖结构的半导体器件，其中包括氧化物半导体的晶体管和包括氧化物半导体之外的半导体材料的晶体管被堆叠。该半导体器件包括第一晶体管，第一晶体管上的绝缘层和绝缘层上的第二晶体管。在半导体器件中，第一晶体管包括第一沟道形成区，第二晶体管包括第二沟道形成区，第一沟道形成区包括与第二沟道形成区的半导体材料不同的半导体材料，绝缘层包括均方根表面粗糙度小于或等于1nm的表面。

54. 发明申请

US20120064677A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120064677A1
公开(公告)日：2012-03-15
申请号：US13225703
申请日：2011-09-06
申请人： Hidekazu MIYAIRI , Koji DAIRIKI , Shunpei YAMAZAKI , Ryo ARASAWA
发明人： Hidekazu MIYAIRI , Koji DAIRIKI , Shunpei YAMAZAKI , Ryo ARASAWA
IPC分类号： H01L21/336
CPC分类号： H01L29/78678 , H01L29/66765 , H01L29/78606 , H01L29/78648 , H01L29/78669 , H01L29/78696
摘要： Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.
摘要翻译：提供一种用于制造具有较少掩模的半导体器件的方法，并且在简单的过程中。形成栅电极。依次层叠栅绝缘膜，半导体膜，杂质半导体膜和导电膜，覆盖栅电极。通过处理导电膜形成源电极和漏电极。通过处理半导体膜的上部，形成源区域，漏极区域和半导体层，其部分的上部不与源极区域和漏极区域重叠，而杂质半导体薄膜被划分。形成栅极绝缘膜，半导体层，源极区域，漏极区域，源极电极和漏极电极之后的钝化膜。在钝化膜上形成蚀刻掩模。通过使用蚀刻掩模，至少钝化膜和半导体层被加工成具有岛状，同时形成到达源电极或漏电极的开口。去除蚀刻掩模。在栅极绝缘膜和钝化膜上形成像素电极。

55. 发明申请

US20120062809A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120062809A1
公开(公告)日：2012-03-15
申请号：US13233120
申请日：2011-09-15
申请人： Chiho KOKUBO , Hirokazu YAMAGATA , Shunpei YAMAZAKI
发明人： Chiho KOKUBO , Hirokazu YAMAGATA , Shunpei YAMAZAKI
IPC分类号： G02F1/133
CPC分类号： H01L21/02672 , G02F1/13454 , G09G3/30 , G09G3/3225 , G09G3/3233 , G09G3/3648 , G09G2300/0842 , G09G2300/0861 , H01L21/02532 , H01L21/2022 , H01L27/12 , H01L27/1248 , H01L27/1255 , H01L27/1277 , H01L27/3244 , H01L29/04 , H01L29/66757 , H01L29/78624 , H01L29/78645 , H01L29/78675
摘要： There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.
摘要翻译：公开了半导体器件和制造半导体器件的方法，其中缩短了晶体生长所需的热处理时间并简化了工艺。两个催化元素引入区域布置在一个有源层的两侧，并进行结晶。在成为源极区域或漏极区域的区域中形成有来自一个催化剂元件导入区域的晶体生长与其他催化剂元素导入区域的晶体生长相交的边界部分。

56. 发明申请

US20120058599A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120058599A1
公开(公告)日：2012-03-08
申请号：US13227585
申请日：2011-09-08
申请人： Shunpei YAMAZAKI , Hidekazu MIYAIRI , Kengo AKIMOTO , Kojiro SHIRAISHI
发明人： Shunpei YAMAZAKI , Hidekazu MIYAIRI , Kengo AKIMOTO , Kojiro SHIRAISHI
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L29/7869 , H01L27/1225
摘要： The semiconductor device includes a thin film transistor which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, a source electrode layer and a drain electrode layer over the gate insulating layer, a buffer layer over the source electrode layer and the drain electrode layer, and a semiconductor layer over the buffer layer. A part of the semiconductor layer overlapping with the gate electrode layer is over and in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer is an oxide semiconductor layer containing indium, gallium, and zinc. The buffer layer contains a metal oxide having n-type conductivity. The semiconductor layer and the source and drain electrode layers are electrically connected to each other through the buffer layer.
摘要翻译：该半导体器件包括薄膜晶体管，该薄膜晶体管包括栅极电极层，栅极电极层上的栅极绝缘层，栅极绝缘层上的源极电极层和漏极电极层，源电极层上的缓冲层和漏极电极层和缓冲层上的半导体层。与栅电极层重叠的半导体层的一部分与栅极绝缘层相接触并且设置在源极电极层和漏极电极层之间。半导体层是含有铟，镓和锌的氧化物半导体层。缓冲层含有具有n型导电性的金属氧化物。半导体层和源极和漏极电极层通过缓冲层彼此电连接。

57. 发明申请

US20120058598A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120058598A1
公开(公告)日：2012-03-08
申请号：US13211588
申请日：2011-08-17
申请人： Shunpei YAMAZAKI
发明人： Shunpei YAMAZAKI
IPC分类号： H01L21/34
CPC分类号： H01L21/02565 , H01L21/02488 , H01L21/02554 , H01L21/02631 , H01L21/283 , H01L29/66969 , H01L29/78603 , H01L29/7869
摘要： Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
摘要翻译：使用氧化物半导体的晶体管的电气特性在基板，基板之间和批次之间变化很大，并且电特性在某些情况下由于热，偏压，光等而改变。鉴于上述，制造了使用具有高可靠性和小的电特性变化的氧化物半导体的半导体器件。在制造半导体器件的方法中，使用氧化物半导体在晶体管中去除膜中的膜和膜之间的界面处的氢。为了在膜之间的界面处除去氢，基板在膜形成之间在真空下转移。此外，对于具有暴露于空气的表面的基板，可以通过热处理或等离子体处理来去除基板表面上的氢。

58. 发明申请

US20120052624A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20120052624A1
公开(公告)日：2012-03-01
申请号：US13211504
申请日：2011-08-17
申请人： Shunpei YAMAZAKI
发明人： Shunpei YAMAZAKI
IPC分类号： H01L21/34
CPC分类号： H01L21/02565 , H01L21/02631 , H01L21/02694 , H01L29/26 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78603 , H01L29/78606 , H01L29/7869
摘要： One object is to have stable electrical characteristics and high reliability and to manufacture a semiconductor device including a semi-conductive oxide film. Film formation is performed by a sputtering method using a target in which gallium oxide is added to a material that is easy to volatilize compared to gallium when the material is heated at 400° C. to 700° C. like zinc, and a formed film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film and the oxide is crystallized. Further, a semi-conductive oxide film is deposited thereover, whereby a semi-conductive oxide having a crystal which succeeds a crystal structure of the oxide that is crystallized by heat treatment is formed.
摘要翻译：一个目的是具有稳定的电特性和高可靠性，并且制造包括半导体氧化膜的半导体器件。当将材料在400℃加热至700℃（如锌）时，使用其中加入氧化镓的靶与易于挥发的材料相比，通过溅射法进行成膜，并且形成膜在400℃加热至700℃，由此将添加的材料分离在膜的表面附近，并使氧化物结晶化。此外，在其上沉积半导电氧化物膜，由此形成具有通过热处理结晶化的氧化物晶体结构成为结晶的半导体氧化物。

59. 发明申请

US20120044433A1 ELECTRO-OPTICAL DEVICE 有权
标题翻译：电光器件
公开(公告)号：US20120044433A1
公开(公告)日：2012-02-23
申请号：US13278219
申请日：2011-10-21
申请人： Yoshiharu HIRAKATA , Takeshi NISHI , Shunpei YAMAZAKI
发明人： Yoshiharu HIRAKATA , Takeshi NISHI , Shunpei YAMAZAKI
IPC分类号： G02F1/1337
CPC分类号： G02F1/13454 , G02F1/1339 , H01L27/12 , H01L27/1214 , H01L27/1248
摘要： In an active matrix semiconductor display device in which pixel TFTs and driver circuit TFT are formed on the same substrate in an integral manner, the cell gap is controlled by gap retaining members that are disposed between a pixel area and driver circuit areas. This makes it possible to provide a uniform cell thickness profile over the entire semiconductor display device. Further, since conventional grainy spacers are not used, stress is not imposed on the driver circuit TFTs when a TFT substrate and an opposed substrate are bonded together. This prevents the driver circuit TFTs from being damaged.
摘要翻译：在其中像素TFT和驱动电路TFT以整体方式形成在同一基板上的有源矩阵半导体显示装置中，通过设置在像素区域和驱动电路区域之间的间隙保持构件来控制单元间隙。这使得可以在整个半导体显示装置上提供均匀的电池厚度分布。此外，由于不使用常规的颗粒状间隔物，当TFT基板和相对的基板接合在一起时，驱动电路TFT不施加应力。这防止驱动电路TFT被损坏。

60. 发明申请

US20120040501A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120040501A1
公开(公告)日：2012-02-16
申请号：US13285256
申请日：2011-10-31
申请人： Shunpei YAMAZAKI
发明人： Shunpei YAMAZAKI
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L27/3262 , H01L21/28114 , H01L27/12 , H01L27/1214 , H01L27/1222 , H01L27/3244 , H01L27/3248 , H01L29/42384 , H01L29/66492 , H01L29/66598 , H01L29/66757 , H01L29/78621 , H01L29/78627 , H01L29/78675 , H01L29/78696 , H01L51/5256 , H01L2029/7863 , H01L2227/32
摘要： There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n−-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n−-type impurity regions overlap with a gate electrode, and the other n−-type impurity regions do not overlap with the gate electrode. Since the two kinds of n−-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.
摘要翻译：提供了具有改进的可靠性的薄膜晶体管。栅电极包括具有锥形部分的第一栅电极和宽度比第一栅电极窄的第二栅电极。半导体层通过第一栅电极掺杂低浓度的磷。在半导体层中，在沟道形成区域和n +型杂质区域之间形成两种n型杂质区域。 n型杂质区域中的一些与栅电极重叠，其他n型杂质区域与栅电极不重叠。由于形成了两种n型杂质区，所以可以减少截止电流，并且可以抑制特性劣化。

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