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51. 发明授权

US07209017B2 Symmetrical linear voltage controlled oscillator 有权
标题翻译：对称线性压控振荡器
公开(公告)号：US07209017B2
公开(公告)日：2007-04-24
申请号：US11048456
申请日：2005-01-31
申请人： Bour-Yi Sze , Chih-Long Ho , Ming-Chieh Huang
发明人： Bour-Yi Sze , Chih-Long Ho , Ming-Chieh Huang
IPC分类号： H03B5/12
CPC分类号： H03L7/10 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03B2201/0266 , H03C3/0958 , H03J5/244 , H03L7/099 , H03L2207/06
摘要： A system is provided to improve frequency stability and system linearity in voltage controlled oscillators. A symmetrical voltage controlled oscillator system embodying the present invention comprises a frequency tuning circuit for receiving a frequency tuning signal, a band tuning circuit coupled with the frequency tuning circuit in a parallel fashion having at least one switching circuit for receiving at least one band tuning signal and at least one switching signal, a core circuit coupled with the frequency tuning circuit and the band tuning circuit for providing a first output and a second output that are complementary to each other, wherein upon asserting the switching signal, and upon adjusting the frequency tuning signal and the band tuning signal, the switching circuit is enabled for configuring the band tuning circuit to join the frequency tuning circuit for determining a predetermined output frequency based on a total inductance and total capacitance provided by the core circuit, the frequency tuning circuit and the band tuning circuit.
摘要翻译：提供一种提高压控振荡器的频率稳定性和系统线性度的系统。体现本发明的对称压控振荡器系统包括用于接收频率调谐信号的频率调谐电路，与频率调谐电路耦合的频带调谐电路，其具有至少一个开关电路，用于接收至少一个频带调谐信号以及至少一个开关信号，与频率调谐电路耦合的核心电路和用于提供彼此互补的第一输出和第二输出的频带调谐电路，其中在断言切换信号时，并且在调整频率调谐信号和频带调谐信号，使开关电路能够配置频带调谐电路，以连接频率调谐电路，用于基于由核心电路，频率调谐电路和频率调谐电路提供的总电感和总电容来确定预定的输出频率带调谐电路。

52. 发明申请

US20100214857A1 MEMORY CIRCUITS, SYSTEMS, AND METHOD OF INTERLEAVING ACCESSES THEREOF 有权
标题翻译：记忆电路，系统及其接入方法
公开(公告)号：US20100214857A1
公开(公告)日：2010-08-26
申请号：US12698423
申请日：2010-02-02
申请人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
发明人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1042 , G11C8/04
摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
摘要翻译：交错存储器电路包括具有第一存储单元的第一存储器组。第一本地控制电路与第一存储体耦合。第二存储器组包括第二存储器单元。第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。全局控制电路与第一和第二本地控制电路耦合。交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一读取列选择信号RSSL用于访问第一个存储单元。

53. 发明授权

US08547779B2 Memory circuits, systems, and method of interleavng accesses thereof 有权
标题翻译：存储器电路，系统及其访问方法
公开(公告)号：US08547779B2
公开(公告)日：2013-10-01
申请号：US13429117
申请日：2012-03-23
申请人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
发明人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
IPC分类号： G11C8/00 , G11C8/18
CPC分类号： G11C7/1042 , G11C8/04
摘要： An interleaved memory circuit includes a memory bank including at least one first memory cell for storing a charge representative of a first datum, the first memory cell being coupled with a first word line and a first bit line. The interleaved memory circuit further includes a local control circuit coupled with the memory bank. The interleaved memory circuit further includes a global control circuit coupled with the local control circuit, an interleaving access including a clock signal having a first cycle and a second cycle for accessing the first memory cell, where the second cycle is capable of enabling the local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
摘要翻译：交织存储器电路包括一个存储体，该存储体包括至少一个用于存储表示第一数据的电荷的第一存储单元，第一存储单元与第一字线和第一位线耦合。交错存储器电路还包括与存储体耦合的本地控制电路。交错存储器电路还包括与本地控制电路耦合的全局控制电路，包括具有用于访问第一存储器单元的第一周期和第二周期的时钟信号的交织访问，其中第二周期能够实现本地控制触发用于访问第一存储器单元的第一读取列选择信号RSSL的第一转换。

54. 发明授权

US08248153B2 Method and apparatus for full clock cycle charge pump operation 有权
标题翻译：全时钟周期电荷泵运行的方法和装置
公开(公告)号：US08248153B2
公开(公告)日：2012-08-21
申请号：US12825423
申请日：2010-06-29
申请人： Ming-Chieh Huang , Bing Wang
发明人： Ming-Chieh Huang , Bing Wang
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , G11C5/145 , H02M2001/0003 , H02M2003/075
摘要： A charge pump comprises at least one charge pump cell and control logic. The at least one charge pump cell is configured to receive a power supply voltage and provide a pump output voltage higher than the power supply voltage. The control logic is configured to receive an oscillator signal and a level detector enable signal, provide at least one cell clock signal, based on the oscillator signal, to the at least one charge pump cell, control the at least one pump cell to charge while the level detector enable signal is asserted, and control the at least one pump cell to continue to charge after the level detector enable signal is deasserted and until a full pulse cycle of the oscillator signal is completed.
摘要翻译：电荷泵包括至少一个电荷泵电池和控制逻辑。所述至少一个电荷泵单元被配置为接收电源电压并提供高于所述电源电压的泵输出电压。控制逻辑被配置为接收振荡器信号和电平检测器使能信号，基于振荡器信号将至少一个单元时钟信号提供给至少一个电荷泵单元，控制至少一个泵浦单元进行充电，同时电平检测器使能信号被断言，并且在电平检测器使能信号被断言并且直到振荡器信号的完整脉冲周期完成之后，控制至少一个泵浦单元继续充电。

55. 发明授权

US08186840B2 Standard illuminant apparatus capable of providing standard LED light 有权
标题翻译：能够提供标准LED灯的标准照明装置
公开(公告)号：US08186840B2
公开(公告)日：2012-05-29
申请号：US12196500
申请日：2008-08-22
申请人： Kuei-Neng Wu , Cheng-Hsien Chen , Chia-Ying Chang , Ming-Chieh Huang
发明人： Kuei-Neng Wu , Cheng-Hsien Chen , Chia-Ying Chang , Ming-Chieh Huang
IPC分类号： G09F13/04
CPC分类号： F21V11/08 , F21V13/12
摘要： A standard illuminant apparatus suitable for providing a standard optical property of LED for measurement is provided. The standard illuminant apparatus comprises an illuminant module and light shape control module, wherein the illuminant module is capable of providing light, and the light shape control module is capable of receiving the light and transforming the light shape of the light to a predetermined light shape as a LED light shape.
摘要翻译：提供了适合于提供用于测量的LED的标准光学特性的标准光源装置。标准照明装置包括光源模块和光形状控制模块，其中，光源模块能够提供光，并且光形状控制模块能够接收光并将光的形状转换成预定的光形状，如 LED灯的形状。

56. 发明授权

US08111107B2 Charge pump control scheme 有权
标题翻译：电荷泵控制方案
公开(公告)号：US08111107B2
公开(公告)日：2012-02-07
申请号：US12831338
申请日：2010-07-07
申请人： Ming-Chieh Huang
发明人： Ming-Chieh Huang
IPC分类号： H03L7/085 , G05F1/10
CPC分类号： H03L7/0995
摘要： An integrated circuit includes a charge pump having a voltage output. A voltage level detector is arranged to receive the voltage output, wherein the voltage level detector provides a first enable signal for the charge pump. A ring oscillator has multiple inverters. The ring oscillator is coupled to the charge pump. A counter control circuit is configured to provide a control signal for adjusting a frequency of the ring oscillator based on the first enable signal of the voltage level detector.
摘要翻译：集成电路包括具有电压输出的电荷泵。电压电平检测器被布置成接收电压输出，其中电压电平检测器为电荷泵提供第一使能信号。环形振荡器有多个反相器。环形振荡器耦合到电荷泵。计数器控制电路被配置为基于电压电平检测器的第一使能信号来提供用于调整环形振荡器的频率的控制信号。

57. 发明授权

US07971492B2 Method and system for inspecting characteristics of bended flexible unit 有权
标题翻译：弯曲柔性单元特性检测方法及系统
公开(公告)号：US07971492B2
公开(公告)日：2011-07-05
申请号：US12126066
申请日：2008-05-23
申请人： Bor-Jiunn Wen , Cheng-Hsien Chen , Zong-Ying Chung , Hsin-Yi Ko , Ming-Chieh Huang
发明人： Bor-Jiunn Wen , Cheng-Hsien Chen , Zong-Ying Chung , Hsin-Yi Ko , Ming-Chieh Huang
IPC分类号： G01N3/20
CPC分类号： G01N21/88 , G01N3/20 , G01N2203/0641
摘要： A method for inspecting characteristics of bended flexible unit is disclosed, which comprises steps of: (a) providing a clip unit, an observing unit, a characteristic-inspecting unit and a controlling unit; said clip unit, observing unit, and characteristic-inspecting unit are electrically connected to said controlling unit which stored a predetermined radius; (b) the clip unit clips a flexible unit and bends the same; (c) the observing unit gets the lateral profile of the flexible unit and sends it to the controlling unit which calculates the bending radius thereof accordingly; and (d) the controlling unit determines if the bending radius is the same to the predetermined one; if positive, the clip unit stops and the characteristic-inspecting unit inspects the characteristic of said flexible unit; if negative, the procedure returns to step (b).
摘要翻译：公开了一种用于检查弯曲柔性单元的特性的方法，其特征在于包括以下步骤：（a）提供夹单元，观察单元，特征检测单元和控制单元; 所述夹持单元，观察单元和特征检查单元电连接到存储预定半径的所述控制单元; （b）夹子单元夹紧柔性单元并使其弯曲; （c）观察单元得到柔性单元的横向轮廓并将其发送到相应地计算其弯曲半径的控制单元; 和（d）控制单元确定弯曲半径是否与预定弯曲半径相同; 如果为正，夹子单元停止，特性检查单元检查所述柔性单元的特性; 如果为负，则过程返回到步骤（b）。

58. 发明授权

US08391094B2 Memory circuits, systems, and operating methods thereof 有权
标题翻译：存储器电路，系统及其操作方法
公开(公告)号：US08391094B2
公开(公告)日：2013-03-05
申请号：US12692534
申请日：2010-01-22
申请人： Ming-Chieh Huang , Kuoyuan Peter Hsu
发明人： Ming-Chieh Huang , Kuoyuan Peter Hsu
IPC分类号： G11C5/04
CPC分类号： G11C5/14 , G11C5/147 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. The memory circuit includes a means for providing a bit line reference voltage VBLref to the bit line, wherein a VBLref/VDD ratio of the bit line reference voltage VBLref to a power voltage VDD is adjustable corresponding to a change of the power voltage VDD.
摘要翻译：存储电路包括至少一个用于存储表示数据的电荷的存储单元。存储单元与字线和位线耦合。存储电路包括用于向位线提供位线参考电压VBLref的装置，其中位线参考电压VBLref与电源电压VDD的VBLref / VDD比可根据电源电压VDD的变化而调节。

59. 发明授权

US08292472B2 Light-emitting device and light-guiding member thereof 有权
标题翻译：发光装置及其导光部件
公开(公告)号：US08292472B2
公开(公告)日：2012-10-23
申请号：US12703145
申请日：2010-02-09
申请人： Ming-Chieh Huang
发明人： Ming-Chieh Huang
IPC分类号： F21V5/00 , F21V13/04
CPC分类号： G02B19/0061 , F21K9/61 , F21V5/04 , F21V7/0091 , F21Y2115/10 , G02B19/0028 , G02B19/0071
摘要： This invention discloses a light-emitting device. The light-emitting device includes a light-guiding member and an LED light source. The light-guiding member includes a reflection surface, a first refraction surface, and a second refraction surface. A first part of light emitted from the LED light source is reflected by the reflection surface and refracted by the first refraction surface to form a first virtual image in the light-guiding member. Moreover, a second part of light emitted from the LED light source is reflected by the reflection surface and refracted by the second refraction surface to form a second virtual image in the light-guiding member.
摘要翻译：本发明公开了一种发光装置。发光装置包括导光部件和LED光源。导光构件包括反射面，第一折射面和第二折射面。从LED光源发出的光的第一部分被反射面反射并被第一折射面折射，以在导光部件中形成第一虚像。此外，从LED光源发射的光的第二部分被反射面反射并被第二折射面折射，以在导光部件中形成第二虚像。

60. 发明授权

US08164974B2 Memory circuits, systems, and method of interleaving accesses thereof 有权
标题翻译：存储器电路，系统及其访问方法
公开(公告)号：US08164974B2
公开(公告)日：2012-04-24
申请号：US12698423
申请日：2010-02-02
申请人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
发明人： Kuoyuan Hsu , Ming-Chieh Huang , Young Suk Kim , Subramani Kengeri
IPC分类号： G11C11/00
CPC分类号： G11C7/1042 , G11C8/04
摘要： An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.
摘要翻译：交错存储器电路包括具有第一存储单元的第一存储器组。第一本地控制电路与第一存储体耦合。第二存储器组包括第二存储器单元。第二本地控制电路与第二存储体耦合。 IO块与第一存储体和第二存储体耦合。全局控制电路与第一和第二本地控制电路耦合。交织接入包括具有第一周期和第二周期的时钟信号，用于分别访问第一存储器单元和第二存储单元，其中第二周期能够使第一本地控制电路触发第一读取列选择信号RSSL用于访问第一个存储单元。

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