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51. 发明申请

US20140021469A1 INTEGRATED CIRCUIT INCLUDING SENSOR STRUCTURE, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：集成电路，包括传感器结构，相关方法和设计结构
公开(公告)号：US20140021469A1
公开(公告)日：2014-01-23
申请号：US13550813
申请日：2012-07-17
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee
IPC分类号： H01L23/48 , H01L21/66
CPC分类号： H01L22/34 , G01R31/2858 , H01L22/30 , H01L23/48 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, an integrated circuit includes: a substrate; a first metal layer disposed on the substrate and including a sensor structure configured to indicate a crack in a portion of the integrated circuit; and a second metal layer disposed proximate the first metal layer, the second metal layer including a wire component disposed proximate the sensor structure.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，集成电路包括：基板; 第一金属层，设置在所述基板上并且包括被构造为指示所述集成电路的一部分中的裂纹的传感器结构; 以及设置在所述第一金属层附近的第二金属层，所述第二金属层包括靠近所述传感器结构设置的导线部件。

52. 发明授权

US08288747B2 Optoelectronic memory devices 有权
标题翻译：光电存储器件
公开(公告)号：US08288747B2
公开(公告)日：2012-10-16
申请号：US12842158
申请日：2010-07-23
申请人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
发明人： Fen Chen , Richard Steven Kontra , Tom C. Lee , Theodore M. Levin , Christopher David Muzzy , Timothy Dooling Sullivan
IPC分类号： H01L29/00 , H01L47/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure. The structure includes a substrate, a resistive/reflective region on the substrate, and a light source/light detecting and/or a sens-amp circuit configured to ascertain a reflectance and/or resistance change in the resistive/reflective region. The resistive/reflective region includes a material having a characteristic of the material's reflectance and/or resistance being changed due to a phase change in the material. The resistive/reflective region is configured to respond, to an electric current through the resistive/reflective region and/or a laser beam projected on the resistive/reflective region, by the phase change in the material which causes a reflectance and/resistance change in the resistive/reflective region from a first reflectance and/or resistance value to a second reflectance and/or resistance value different from the first reflectance and/or resistance value.
摘要翻译：一个结构。该结构包括衬底，衬底上的电阻/反射区域以及被配置为确定电阻/反射区域中的反射率和/或电阻变化的光源/光检测和/或感测放大器电路。电阻/反射区域包括具有材料的反射率和/或电阻的特性的材料由于材料的相变而改变。电阻/反射区域被配置为通过材料的相变来响应通过电阻/反射区域的电流和/或投射在电阻/反射区域上的激光束，这导致反射和/ 电阻/反射区域从第一反射率和/或电阻值到不同于第一反射率和/或电阻值的第二反射率和/或电阻值。

53. 发明申请

US20120146179A1 ELECTRICAL FUSE WITH A CURRENT SHUNT 有权
标题翻译：电流保险丝与电流分流器
公开(公告)号：US20120146179A1
公开(公告)日：2012-06-14
申请号：US12967308
申请日：2010-12-14
申请人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
发明人： Tom C. Lee , Thomas L. McDevitt , William J. Murphy
IPC分类号： H01L23/62 , H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrical fuses and methods for forming an electrical fuse. The electrical fuse includes a current shunt formed by patterning a first layer comprised of a first conductive material and disposed on a top surface of a dielectric layer. A layer stack is formed on the current shunt and the top surface of the dielectric layer surrounding the current shunt. The layer stack includes a second layer comprised of a second conductive material and a third layer comprised of a third conductive material. The layer stack may be patterned to define a fuse link as a first portion of the layer stack directly contacting the top surface of the dielectric layer and a terminal as a second portion separated from the top surface of the dielectric layer by the current shunt.
摘要翻译：电熔丝和形成电熔丝的方法。电熔丝包括通过图案化由第一导电材料构成的第一层并且设置在电介质层的顶表面上而形成的电流分流器。在电流分路上形成层叠层，并且在电流分路周围形成介电层的顶表面。层叠包括由第二导电材料构成的第二层和由第三导电材料构成的第三层。层叠体可以被图案化以限定作为层叠体的第一部分的熔丝链，其直接接触电介质层的顶表面，并且通过电流分路与端子作为与电介质层的顶表面分离的第二部分。

54. 发明申请

US20120012976A1 FUSE STRUCTURE HAVING CRACK STOP VOID, METHOD FOR FORMING AND PROGRAMMING SAME, AND DESIGN STRUCTURE 有权
标题翻译：具有断裂停止的保险丝结构，其形成和编程方法以及设计结构
公开(公告)号：US20120012976A1
公开(公告)日：2012-01-19
申请号：US12838850
申请日：2010-07-19
申请人： Jeffrey P. Gambino , Tom C. Lee , Kevin G. Petrunich , David C. Thomas
发明人： Jeffrey P. Gambino , Tom C. Lee , Kevin G. Petrunich , David C. Thomas
IPC分类号： H01L29/86 , G06F9/45 , H01L21/326 , H01L21/02
CPC分类号： H01L27/11206 , H01L23/5258 , H01L27/112 , H01L2924/0002 , H01L2924/00
摘要： The disclosure relates generally to fuse structures, methods of forming and programming the same, and more particularly to fuse structures having crack stop voids. The fuse structure includes a semiconductor substrate having a dielectric layer thereon and a crack stop void. The dielectric layer includes at least one fuse therein and the crack stop void is adjacent to two opposite sides of the fuse, and extends lower than a bottom surface and above a top surface of the fuse. The disclosure also relates to a design structure of the aforementioned.
摘要翻译：本公开一般涉及熔丝结构，其形成和编程的方法，更具体地涉及具有裂纹停止空隙的熔断结构。熔丝结构包括其上具有介电层的半导体衬底和裂纹阻挡空隙。电介质层包括至少一个熔断器，裂纹阻挡空隙与保险丝的两个相对的两侧相邻，并且比底表面和保险丝顶表面之上延伸。本公开还涉及上述的设计结构。

55. 发明申请

US20110045644A1 FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE 有权
公开(公告)号：US20110045644A1
公开(公告)日：2011-02-24
申请号：US12939538
申请日：2010-11-04
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

56. 发明授权

US07890893B2 Design structure for semiconductor on-chip repair scheme for negative bias temperature instability 有权
标题翻译：用于负偏压温度不稳定性的半导体片上修复方案的设计结构
公开(公告)号：US07890893B2
公开(公告)日：2011-02-15
申请号：US12050990
申请日：2008-03-19
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L23/345 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了一种用于半导体芯片结构的设计结构，其包含由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件的局部的片上修复方案。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

57. 发明授权

US07838958B2 Semiconductor on-chip repair scheme for negative bias temperature instability 有权
标题翻译：半导体片上修复方案负偏温度不稳定性
公开(公告)号：US07838958B2
公开(公告)日：2010-11-23
申请号：US11971937
申请日：2008-01-10
申请人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
发明人： Ronald J. Bolam , Tom C. Lee , Timothy D. Sullivan
IPC分类号： H01L31/058 , H01L37/00 , H01L21/00
CPC分类号： H01L23/345 , H01L22/14 , H01L22/20 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor chip structure and a method that incorporate a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heating element above each device. The heating element is configured so that it can receive transmission line pulses and, thereby generate enough heat to raise the adjacent device to a temperature sufficient to allow for performance recovery. Specifically, high temperatures (e.g., between approximately 300-400° C. or greater) in the absence of bias can accelerate the recovery process to a matter of seconds as opposed to days or months. The heating element can be activated, for example, on demand, according to a pre-set service schedule, and/or in response to feedback from a device performance monitor.
摘要翻译：公开了半导体芯片结构的实施例和一种对于由于负偏压温度不稳定性（NBTI）而表现出性能劣化的器件而并入局部的片上修复方案的方法。修理方案在每个设备上使用加热元件。加热元件被配置成使得其可以接收传输线脉冲，并且由此产生足够的热量以将相邻设备升高到足以允许性能恢复的温度。具体而言，在不存在偏压的情况下，高温（例如，约300-400℃或更高）可以将恢复过程加速到几秒钟，而不是几天或几个月。加热元件例如可以根据预先设定的服务时间表和/或响应于来自设备性能监视器的反馈而被激活。

58. 发明授权

US07768815B2 Optoelectronic memory devices 失效
标题翻译：光电存储器件
公开(公告)号：US07768815B2
公开(公告)日：2010-08-03
申请号：US11161941
申请日：2005-08-23
申请人： Fen Chen , Richard S. Kontra , Tom C. Lee , Theodore M. Levin , Christopher D. Muzzy , Timothy D. Sullivan
发明人： Fen Chen , Richard S. Kontra , Tom C. Lee , Theodore M. Levin , Christopher D. Muzzy , Timothy D. Sullivan
IPC分类号： G11C13/00
CPC分类号： G11C13/0009 , G11C13/0004 , G11C13/004 , G11C13/04 , G11C13/047 , G11C2013/0054 , H01L45/1213 , H01L45/145
摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.
摘要翻译：一种结构及其操作方法。该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

59. 发明授权

US07639032B2 Structure for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力导致退化的结构
公开(公告)号：US07639032B2
公开(公告)日：2009-12-29
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence A. Clevenger , Andrew P. Cowley , Ronald G. Filippi , Jason P. Gill , Tom C. Lee , Baozhen Li , Paul S. McLaughlin , Du B. Nguyen , Hazara S. Rathore , Timothy D. Sullivan , Chih-Chao Yang
IPC分类号： G01R31/02 , H01L23/58 , G01N25/20
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

60. 发明授权

US08765595B2 Thick on-chip high-performance wiring structures 有权
标题翻译：厚片上高性能布线结构
公开(公告)号：US08765595B2
公开(公告)日：2014-07-01
申请号：US13345120
申请日：2012-01-06
申请人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
发明人： Edward C. Cooney, III , Jeffrey P. Gambino , Zhong-Xiang He , Tom C. Lee , Xiao H. Liu
IPC分类号： H01L21/4763
CPC分类号： H01L23/5227 , H01L21/76883 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.
摘要翻译： BEOL布线结构的制造方法，BEOL布线结构以及BEOL布线结构的设计结构。 BEOL布线可以通过在电介质层中形成第一布线并在无氧气氛中退火第一布线来制造。在第一线退火之后，形成与第一线垂直对准的第二线。形成由诸如聚酰亚胺的有机材料组成的最终钝化层，其覆盖第二线的整个侧壁。

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