专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US08232606B2 High-K dielectric and metal gate stack with minimal overlap with isolation region 有权
标题翻译：高K电介质和金属栅极堆叠与隔离区域重叠
公开(公告)号：US08232606B2
公开(公告)日：2012-07-31
申请号：US13150378
申请日：2011-06-01
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey Sleight
IPC分类号： H01L29/76
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

52. 发明授权

US08105892B2 Thermal dual gate oxide device integration 有权
标题翻译：热双栅氧化器器件集成
公开(公告)号：US08105892B2
公开(公告)日：2012-01-31
申请号：US12542768
申请日：2009-08-18
申请人： Byeong Y. Kim , Michael P. Chudzik
发明人： Byeong Y. Kim , Michael P. Chudzik
IPC分类号： H01L21/8238
CPC分类号： H01L27/0922 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/1054 , H01L29/517 , H01L29/7833
摘要： A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.
摘要翻译：提供了一种方法，其包括提供至少包括薄栅极氧化物pFET器件区域和厚栅极氧化物pFET器件区域的半导体衬底，并在薄栅极氧化物pFET器件区域内形成薄栅极氧化物pFET，并在其内形成厚栅极氧化物pFET 厚栅氧化物pFET器件区域。所形成的薄栅氧化物pFET包括在薄栅极氧化物pFET器件区域的上表面上的SiGe层，位于SiGe层的上表面上的高k栅极电介质，pFET阈值电压调节层，位于高k栅极电介质的上表面，以及pFET阈值电压调节层顶部的栅极导体材料。形成的厚栅极氧化物pFET包括位于厚栅极氧化物pFET器件区域的上表面上的热氧化物，位于热氧化物的上表面上的硅层和位于硅层顶部的栅极导体材料。

53. 发明授权

US08021939B2 High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods 失效
标题翻译：高k介质和金属栅极堆叠与隔离区域和相关方法的重叠最小
公开(公告)号：US08021939B2
公开(公告)日：2011-09-20
申请号：US11954775
申请日：2007-12-12
申请人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
发明人： Michael P. Chudzik , William K. Henson , Renee T. Mo , Jeffrey W Sleight
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28123 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
摘要翻译：公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

54. 发明申请

US20100244206A1 METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS 审中-公开
标题翻译：用于高K金属栅极晶体管的阈值电压控制和驱动电流改进的方法和结构
公开(公告)号：US20100244206A1
公开(公告)日：2010-09-30
申请号：US12414794
申请日：2009-03-31
申请人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
发明人： Huiming Bu , Michael P. Chudzik , Wei He , Rashmi Jha , Young-Hee Kim , Siddarth A. Krishnan , Renee T. Mo , Naim Moumen , Wesley C. Natzle
IPC分类号： H01L23/00 , H01L21/314
CPC分类号： H01L21/28202 , H01L21/28176 , H01L21/28185 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.
摘要翻译：形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

55. 发明申请

US20100181630A1 DIRECT CONTACT BETWEEN HIGH-K/METAL GATE AND WIRING PROCESS FLOW 有权
标题翻译：高K /金属门与接线工艺流程之间的直接接触
公开(公告)号：US20100181630A1
公开(公告)日：2010-07-22
申请号：US12355953
申请日：2009-01-19
申请人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
发明人： Huiming Bu , Michael P. Chudzik , Ricardo A. Donaton , Naim Moumen , Hongwen Yan
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/4958 , H01L21/28079 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A low resistance contact is formed to a metal gate or a transistor including a High-K gate dielectric in a high integration density integrated circuit by applying a liner over a gate stack, applying a fill material between the gate stacks, planarizing the fill material to support high-resolution lithography, etching the fill material and the liner selectively to each other to form vias and filling the vias with a metal, metal alloy or conductive metal compound such as titanium nitride.
摘要翻译：通过在栅极堆叠上施加衬垫，在栅堆叠之间施加填充材料，将填充材料平坦化，将填充材料平坦化，形成低电阻接触到金属栅极或包括高集成度密度集成电路中的高K栅极电介质的晶体管支持高分辨率光刻，相互选择性地蚀刻填充材料和衬垫以形成通孔并用金属，金属合金或导电金属化合物如氮化钛填充通孔。

56. 发明申请

US20090280631A1 Electroless Metal Deposition For Dual Work Function 失效
标题翻译：无功金属沉积双功能功能
公开(公告)号：US20090280631A1
公开(公告)日：2009-11-12
申请号：US12117769
申请日：2008-05-09
申请人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
发明人： Jeffrey P. Gambino , Michael P. Chudzik , Renee T. Mo
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/82345 , H01L21/823462 , H01L29/4966 , H01L29/517
摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.
摘要翻译：本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

57. 发明授权

US07569466B2 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US07569466B2
公开(公告)日：2009-08-04
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
发明人： Alessandro C. Callegari , Michael P. Chudzik , Bruce B. Doris , Vijay Narayanan , Vamsi K. Paruchuri , Michelle L. Steen
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

58. 发明申请

US20080258198A1 STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS 审中-公开
标题翻译：用于CMOS的基于氧化铝的硅晶体管中的平坦电压稳压和阈值电压稳定
公开(公告)号：US20080258198A1
公开(公告)日：2008-10-23
申请号：US12166690
申请日：2008-07-02
申请人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk , Michael P. Chudzik , Matthew W. Copel , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L29/76
CPC分类号： H01L21/28167 , H01L21/28185 , H01L21/28194 , H01L29/4966 , H01L29/517
摘要： The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising: a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.
摘要翻译：本发明提供一种金属堆叠结构，其稳定包括含Si导体和Hf基电介质的材料堆叠的平带电压和阈值电压。本发明通过将含稀土金属的层引入材料堆中来稳定平带电压和阈值电压，其通过电负性差异将阈值电压的偏移引入期望的电压。具体地说，本发明提供了一种金属叠层，包括：铪基电介质; 位于所述铪基电介质的顶部或内部的含稀土金属的层; 位于所述铪基电介质上方的导电覆盖层; 和含Si导体。

59. 发明申请

US20080249650A1 METHOD FOR COMPOSITION CONTROL OF A METAL COMPOUND FILM 失效
标题翻译：金属化合物膜的组成控制方法
公开(公告)号：US20080249650A1
公开(公告)日：2008-10-09
申请号：US11696507
申请日：2007-04-04
申请人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Russell D. Allen , Stephen L. Brown , Alessandro C. Callegari , Michael P. Chudzik , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： G06F19/00 , G01N21/00
CPC分类号： G01N21/8422 , G01N21/59 , H01L22/12 , H01L22/20
摘要： Measurement of the extinction coefficient k is employed for effective and prompt in-line monitoring and/or controlling of the metal film composition. The dependency of the extinction coefficient on the composition of a metal compound is characterized by measuring the extinction coefficients of a series of the metal compound with different compositions. A monitor metal film is then deposited on a wafer. The extinction coefficient k of the film on the wafer is measured and a film compositional parameter is extracted. The wafer processing may continue if k is in specification or the needed compositional change in the film may be extracted from the measured value of the k and the established dependence of k on the composition of the film for out-of-spec k values.
摘要翻译：使用消光系数k的测量来有效且迅速地在线监测和/或控制金属膜组合物。消光系数对金属化合物的组成的依赖性的特征在于测量一系列具有不同组成的金属化合物的消光系数。然后将监测金属膜沉积在晶片上。测量晶片上的膜的消光系数k并提取膜组成参数。如果k在规范中，则可以继续进行晶片处理，或者可以从k的测量值中提取所需的胶片组成变化，并且建立k的关于对于超出规格k值的胶片的组成的依赖性。

60. 发明申请

US20080203485A1 STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有改进的通道移动性的CMOS器件的应变金属栅结构及其形成方法
公开(公告)号：US20080203485A1
公开(公告)日：2008-08-28
申请号：US11680108
申请日：2007-02-28
申请人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
发明人： Michael P. Chudzik , Wei He , Renee T. Mo , Naim Moumen , Vijay Narayanan , Dae-gyu Park , Vamsi Paruchuri
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/78 , H01L29/7845
摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.
摘要翻译：用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式