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51. 发明授权

US08368125B2 Multiple orientation nanowires with gate stack stressors 失效
标题翻译：具有栅堆叠应力的多取向纳米线
公开(公告)号：US08368125B2
公开(公告)日：2013-02-05
申请号：US12505580
申请日：2009-07-20
申请人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
发明人： Dureseti Chidambarrao , Xiao Hu Liu , Lidija Sekaric
IPC分类号： H01L27/085
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/0673 , H01L29/517 , H01L29/518 , H01L29/7842 , H01L29/7845
摘要： An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness tC; and a dielectric film of thickness tg in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.
摘要翻译：电子器件包括限定晶体结构且具有长度和厚度tC的导电沟道; 以及与沟道的表面接触的厚度为tg的电介质膜。此外，膜包括在通道的接触表面上施加压缩力或拉力中的一种的材料，使得沿着通道长度的电荷载流子（电子或空穴）的电迁移率由于压缩或拉伸力而增加取决于通道长度相对于晶体结构的对准。给出了在不同晶体管中空穴和电子迁移率增加的芯片的实施例，以及制造这种晶体管或芯片的方法。

52. 发明授权

US08299622B2 IC having viabar interconnection and related method 有权
标题翻译： IC具有viabar互连及相关方法
公开(公告)号：US08299622B2
公开(公告)日：2012-10-30
申请号：US12186061
申请日：2008-08-05
申请人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
发明人： Dureseti Chidambarrao , Stephen E. Greco , Kia S. Low
IPC分类号： H01L23/52
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.
摘要翻译：一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar，在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

53. 发明授权

US08296691B2 Methodology for improving device performance prediction from effects of active area corner rounding 失效
标题翻译：从活动区域四舍五入的角度提高设备性能预测的方法
公开(公告)号：US08296691B2
公开(公告)日：2012-10-23
申请号：US11971015
申请日：2008-01-08
申请人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Gerald M. Davidson , Paul A. Hyde , Judith H. McCullen , Shreesh Narasimha
IPC分类号： G06F17/50 , G06F9/45 , G06G7/48
CPC分类号： G06F17/5036
摘要： A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value. A netlist used in a simulation includes the deltaW adder values to more accurately describe the characteristics of the transistor device being modeled including modeling of lithographic corner rounding effect on transistor device parametrics.
摘要翻译：一种用于建模半导体晶体管器件结构的系统和方法，所述半导体晶体管器件结构具有设计长度的导线特征，所述导线特征与待建模的电路中的晶体管器件的栅极连接，所述晶体管包括有源器件（RX）形成并且其上延伸有导线特征。该方法包括提供分析模型表示，其包括用于建模影响有源器件区域宽度的光刻火炬效应的功能; 并且从建模功能将有源器件区域宽度（deltaW加法器）的有效变化与距离RX区域的限定边缘的距离的函数相关联。然后，器件的晶体管紧凑型模型中的晶体管模型参数值被更新为包括要添加到内置deltaW值的ΔW加法器值。在模拟中使用的网表包括deltaW加法器值，以更精确地描述被建模的晶体管器件的特性，包括对晶体管器件参数的光刻拐角舍入效应的建模。

54. 发明申请

US20120261672A1 MINIMIZING LEAKAGE CURRENT AND JUNCTION CAPACITANCE IN CMOS TRANSISTORS BY UTILIZING DIELECTRIC SPACERS 失效
标题翻译：通过使用电介质间隔来最小化CMOS晶体管的漏电流和结电容
公开(公告)号：US20120261672A1
公开(公告)日：2012-10-18
申请号：US13084594
申请日：2011-04-12
申请人： Dureseti Chidambarrao , Ramachandran Muralidhar , Philip J. Oldiges , Viorel Ontalus
发明人： Dureseti Chidambarrao , Ramachandran Muralidhar , Philip J. Oldiges , Viorel Ontalus
IPC分类号： H01L27/092 , H01L21/782 , H01L21/8238 , H01L27/12
CPC分类号： H01L21/823814 , H01L21/3086 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L21/84
摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.
摘要翻译：公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。最小化晶体管结电容可以提高CMOS晶体管的开关速度。因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

55. 发明授权

US08176444B2 Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance 有权
标题翻译：分析多个诱导的系统和统计布局对电路性能的影响
公开(公告)号：US08176444B2
公开(公告)日：2012-05-08
申请号：US12426475
申请日：2009-04-20
申请人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
发明人： Shayak Banerjee , Dureseti Chidambarrao , James A. Culp , Praveen Elakkumanan , Saibal Mukhopadhyay
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.
摘要翻译：一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

56. 发明授权

US08168489B2 High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture 有权
标题翻译：使用Si：C和SiGe外延源/漏极的高性能应力增强MOSFETs及其制造方法
公开(公告)号：US08168489B2
公开(公告)日：2012-05-01
申请号：US11782429
申请日：2007-07-24
申请人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/3081 , H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/1054 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
摘要翻译：半导体器件及半导体器件的制造方法。半导体器件包括用于pFET和nFET的沟道。在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。

57. 发明授权

US08119472B2 Silicon device on Si:C SOI and SiGe and method of manufacture 有权
标题翻译： Si：C SOI和SiGe上的硅器件及其制造方法
公开(公告)号：US08119472B2
公开(公告)日：2012-02-21
申请号：US11757883
申请日：2007-06-04
申请人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
发明人： Dureseti Chidambarrao , Omer H. Dokumaci , Oleg G. Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/1608 , H01L21/8213 , H01L21/823412 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/1054 , H01L29/1095 , H01L29/66651 , H01L29/7378 , H01L29/7843 , H01L29/7846 , H01L29/7849 , H01L29/8086
摘要： A semiconductor structure and method of manufacturing is provided. The method of manufacturing includes forming shallow trench isolation (STI) in a substrate and providing a first material and a second material on the substrate. The first material and the second material are mixed into the substrate by a thermal anneal process to form a first island and second island at an nFET region and a pFET region, respectively. A layer of different material is formed on the first island and the second island. The STI relaxes and facilitates the relaxation of the first island and the second island. The first material may be deposited or grown Ge material and the second material may deposited or grown Si:C or C. A strained Si layer is formed on at least one of the first island and the second island.
摘要翻译：提供半导体结构和制造方法。制造方法包括在衬底中形成浅沟槽隔离（STI），并在衬底上提供第一材料和第二材料。第一材料和第二材料通过热退火工艺混合到衬底中，以分别在nFET区和pFET区形成第一岛和第二岛。在第一岛和第二岛上形成不同材料的层。科学技术组织放松并促进第一个岛屿和第二个岛屿的放松。可以将第一材料沉积或生长Ge材料，并且第二材料可以沉积或生长Si：C或C.在第一岛和第二岛中的至少一个上形成应变Si层。

58. 发明授权

US08013397B2 Embedded stressed nitride liners for CMOS performance improvement 有权
标题翻译：嵌入式应力氮化物衬垫可提高CMOS性能
公开(公告)号：US08013397B2
公开(公告)日：2011-09-06
申请号：US12049450
申请日：2008-03-17
申请人： Dureseti Chidambarrao , Omer H. Dokumaci
发明人： Dureseti Chidambarrao , Omer H. Dokumaci
IPC分类号： H01L27/00
CPC分类号： H01L21/823807 , H01L21/28247 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate region positioned on a mesa portion of a substrate; and a nitride liner positioned on the gate region and recessed surfaces of the substrate adjacent to the gate region, the nitride liner providing a stress to a device channel underlying the gate region. The stress produced on the device channel is a longitudinal stress on the order of about 275 MPa to about 450 MPa.
摘要翻译：本发明提供了一种半导体器件，其包括位于衬底的台面部分上的栅极区域; 以及位于所述栅极区域上的氮化物衬垫和与所述栅极区域相邻的所述衬底的凹陷表面，所述氮化物衬垫向所述栅极区域下方的器件沟道施加压力。在器件通道上产生的应力是大约275MPa至大约450MPa的纵向应力。

59. 发明授权

US08004059B2 eFuse containing SiGe stack 有权
标题翻译： eFuse包含SiGe堆栈
公开(公告)号：US08004059B2
公开(公告)日：2011-08-23
申请号：US11622616
申请日：2007-01-12
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

60. 发明授权

US07989233B2 Semiconductor nanowire with built-in stress 失效
公开(公告)号：US07989233B2
公开(公告)日：2011-08-02
申请号：US13004340
申请日：2011-01-11
申请人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
发明人： Lidija Sekaric , Dureseti Chidambarrao , Xiao H. Liu
IPC分类号： H01L29/06
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/517 , H01L29/66439 , H01L29/7843 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A semiconductor nanowire having two semiconductor pads on both ends is suspended over a substrate. Stress-generating liner portions are formed over the two semiconductor pads, while a middle portion of the semiconductor nanowire is exposed. A gate dielectric and a gate electrode are formed over the middle portion of the semiconductor nanowire while the semiconductor nanowire is under longitudinal stress due to the stress-generating liner portions. The middle portion of the semiconductor nanowire is under a built-in inherent longitudinal stress after removal of the stress-generating liners because the formation of the gate dielectric and the gate electrode locks in the strained state of the semiconductor nanowire. Source and drain regions are formed in the semiconductor pads to provide a semiconductor nanowire transistor. A middle-of-line (MOL) dielectric layer may be formed directly on the source and drain pads.

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