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51. 发明授权

US08471739B2 Digital analog converter and method for calibrating sources thereof 失效
标题翻译：数字模拟转换器及其源的校准方法
公开(公告)号：US08471739B2
公开(公告)日：2013-06-25
申请号：US13312449
申请日：2011-12-06
申请人： Jang Hong Choi , Hyun Kyu Yu
发明人： Jang Hong Choi , Hyun Kyu Yu
IPC分类号： H03M1/10
CPC分类号： H03M1/0653 , H03M1/685 , H03M1/747
摘要： Provided is a digital analog converter that output currents having different magnitudes for a digital input value according to a mapping table. The digital analog converter includes: a plurality of current sources; and a calibration unit configured to sort index values for identifying the plurality of current sources according to current magnitudes of the current sources, couple each two current sources which are symmetrical left and right about the center of the sorted index values, and map the current source pairs into a mapping table.
摘要翻译：提供了一种数字模拟转换器，其根据映射表输出对数字输入值具有不同幅度的电流。数字模拟转换器包括：多个电流源; 以及校准单元，被配置为根据当前源的当前幅度对用于识别多个电流源的索引值进行排序，将关于分选的索引值的中心的左右对称的两个电流源耦合，并且将当前源成对映射表。

52. 发明授权

US08295405B2 Apparatus and method for I/Q mismatch calibration 有权
标题翻译：用于I / Q不匹配校准的装置和方法
公开(公告)号：US08295405B2
公开(公告)日：2012-10-23
申请号：US12629018
申请日：2009-12-01
申请人： Hyun Kyu Yu , Mun Yang Park , Jae Hoon Shim
发明人： Hyun Kyu Yu , Mun Yang Park , Jae Hoon Shim
IPC分类号： H04L27/22
CPC分类号： H04L27/3863
摘要： There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals.
摘要翻译：提供了用于同相/正交相（I / Q）不匹配校准的装置和方法。该装置包括：对称点提取部分，接收连续波信号并提取连续波信号的I / Q信道平均轨迹; 从所提取的I / Q通道平均轨迹提取连续波信号的失真程度的误差提取部分; 以及使用连续波信号的失真程度来校准连续波信号的I信道信号和Q信道信号之间的失配的校准部分。

53. 发明授权

US08274420B2 Successive approximation analog-to-digital converter 有权
标题翻译：逐次近似模数转换器
公开(公告)号：US08274420B2
公开(公告)日：2012-09-25
申请号：US12970861
申请日：2010-12-16
申请人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
发明人： Hyun Kyu Yu , Seon Ho Han , Young Hwa Kim , Seong Hwan Cho
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/827
摘要： There is provided a successive approximation analog-to-digital converter including only minimal capacitors to perform an analog-to-digital conversion operation, thereby making it possible to have very strong process change resistance characteristics while having reduced capacitance and circuit area. The successive approximation analog-to-digital converter may include a reference current supplying unit that supplies a reference current; a signal storage unit that stores a reference signal generated by charging the reference current and an input signal input from the outside; a comparing unit that compares the reference signal and the input signal; and a controller that controls the reference current supplying unit while generating the digital output signal based on the comparison result of the comparing unit to change the supply amount of the reference current supplied to the signal storage unit in proportion to the binary code.
摘要翻译：提供了仅包括最小电容器以执行模数转换操作的逐次逼近模数转换器，从而使得可以具有非常强的工艺变化电阻特性，同时具有减小的电容和电路面积。逐次逼近模数转换器可以包括提供参考电流的参考电流提供单元; 信号存储单元，存储通过对参考电流进行充电而产生的参考信号和从外部输入的输入信号; 比较单元，其比较所述参考信号和所述输入信号; 以及控制器，其基于所述比较单元的比较结果来控制所述参考电流供给单元，同时根据所述二进制码来改变提供给所述信号存储单元的参考电流的供给量。

54. 发明申请

US20120146852A1 PULSE RADAR RECEIVER 有权
标题翻译：脉冲雷达接收器
公开(公告)号：US20120146852A1
公开(公告)日：2012-06-14
申请号：US13316381
申请日：2011-12-09
申请人： Pil Jae Park , Seong Do Kim , Sung Chul Woo , Hyun Kyu Yu
发明人： Pil Jae Park , Seong Do Kim , Sung Chul Woo , Hyun Kyu Yu
IPC分类号： G01S7/285
CPC分类号： G01S7/292
摘要： A pulse radar receiver includes a power splitter configured to split a transmit (TX) trigger signal for generating a TX pulse, a phase-locked loop (PLL) configured to receive a division ratio and the TX trigger signal split by the power splitter, and generate a sampling frequency, and a sampler configured to sample a reflected wave received through an RX antenna, according to the sampling frequency generated by the PLL. Accordingly, it is possible to provide a high distance resolution by generating a sampling frequency with a difference from a TX pulse to sample a reflected wave received through an RX antenna. Thus, it is possible to overcome a limitation in the distance resolution due to the pulse width and to measure a minute movement at a short distance. Therefore, the pulse radar receiver is applicable to high range resolution radar applications such as a living body measuring radar.
摘要翻译：脉冲雷达接收机包括：功率分配器，被配置为分离用于产生TX脉冲的发射（TX）触发信号;配置为接收分频比的锁相环（PLL）和由功率分配器分离的TX触发信号;以及产生采样频率，并且采样器被配置为根据由PLL产生的采样频率对通过RX天线接收的反射波进行采样。因此，通过产生与TX脉冲不同的采样频率来采样通过RX天线接收的反射波，可以提供高距离分辨率。因此，可以克服由于脉冲宽度导致的距离分辨率的限制并且能够在短距离处测量微小的移动。因此，脉冲雷达接收机适用于诸如生物体测量雷达的高范围分辨率雷达应用。

55. 发明授权

US07994851B2 PSK demodulator using time-to-digital converter 失效
标题翻译： PSK解调器采用时间 - 数字转换器
公开(公告)号：US07994851B2
公开(公告)日：2011-08-09
申请号：US12511323
申请日：2009-07-29
申请人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
发明人： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
IPC分类号： H04L27/06 , H03D3/18
CPC分类号： H04L27/233 , H04L27/2338
摘要： A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
摘要翻译：使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。可以降低功耗并简化电路实现。

56. 发明授权

US07973368B2 Semiconductor device with T-gate electrode 失效
标题翻译：具有T型栅电极的半导体器件
公开(公告)号：US07973368B2
公开(公告)日：2011-07-05
申请号：US12122982
申请日：2008-05-19
申请人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim , Hyun Kyu Yu
发明人： Jong Won Lim , Ho Kyun Ahn , Hong Gu Ji , Woo Jin Chang , Jae Kyoung Mun , Hae Cheon Kim , Hyun Kyu Yu
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/778 , H01L29/20 , H01L29/42316 , H01L29/66462
摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.
摘要翻译：提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

57. 发明申请

US20100134334A1 METHOD AND DEVICE FOR DIGITALLY CORRECTING DC OFFSET 有权
标题翻译：用于数字校正直流偏置的方法和装置
公开(公告)号：US20100134334A1
公开(公告)日：2010-06-03
申请号：US12628186
申请日：2009-11-30
申请人： Jae Hoon SHIM , Hyun Kyu Yu
发明人： Jae Hoon SHIM , Hyun Kyu Yu
IPC分类号： H03M1/06
CPC分类号： H03F3/005
摘要： There is provided a digital Direct Current (DC) offset correction method and device. The device includes a digital-analog converter charging a load capacitor according to an input code value and generating an initial voltage value of the load capacitor; a comparator comparing an output DC offset value of a discrete-time amplifier and filter on the basis of the initial voltage value with a preset output DC offset value when the discrete-time amplifier and filter and the load capacitor are connected to each other; and a controller changing the input code value of the digital-analog converter according to comparison result of the comparator.
摘要翻译：提供了数字直流（DC）偏移校正方法和装置。该装置包括数模转换器，根据输入代码值对负载电容器充电并产生负载电容器的初始电压值; 当离散时间放大器和滤波器和负载电容器彼此连接时，比较器将基于初始电压值的离散时间放大器和滤波器的输出DC偏移值与预设输出DC偏移值进行比较; 以及根据比较器的比较结果改变数模转换器的输入代码值的控制器。

58. 发明授权

US07626476B2 Multi-metal coplanar waveguide 有权
标题翻译：多金属共面波导
公开(公告)号：US07626476B2
公开(公告)日：2009-12-01
申请号：US11690219
申请日：2007-03-23
申请人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
发明人： Cheon Soo Kim , Myung Shin Kwak , Seong Do Kim , Mun Yang Park , Hyun Kyu Yu , Hee Bum Jung
IPC分类号： H01P3/08
CPC分类号： H01P3/003
摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.
摘要翻译：提供了一种使用多层互连CMOS技术的共面波导CPW。在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。结果，可以提高超高频电路的性能并使电路小型化。

59. 发明授权

US07626473B2 Signal transmission line for millimeter-wave band 有权
标题翻译：毫米波段信号传输线
公开(公告)号：US07626473B2
公开(公告)日：2009-12-01
申请号：US11872026
申请日：2007-10-14
申请人： Ho Young Kim , Hae Cheon Kim , Hyun Kyu Yu , Young Jun Chong
发明人： Ho Young Kim , Hae Cheon Kim , Hyun Kyu Yu , Young Jun Chong
IPC分类号： H01P5/02 , H01P3/08
CPC分类号： H01P3/00
摘要： Provided is a signal transmission line for a millimeter-wave band. The signal transmission line includes: a dielectric substrate; an input line formed on the dielectric substrate; a pair of serial transmission lines formed on the dielectric substrate, the serial transmission lines being branched at, separated from, and electromagnetically connected in series with one end of the input line; a pair of parallel transmission lines respectively formed on the dielectric substrate at both sides of the input line and the serial transmission lines, and having both ends separated from and electromagnetically connected in parallel with one end of each of the input line and the serial transmission lines; and a pair of wires electrically connected between the other ends of the parallel transmission lines and a connection pad of a monolithic microwave integrated circuit (MMIC). An electrical signal of about 57 to 63 GHz generated from a monolithic microwave integrated circuit (MMIC) can be efficiently transferred.
摘要翻译：提供了一种用于毫米波段的信号传输线。信号传输线包括：电介质基片; 形成在电介质基板上的输入线; 形成在电介质基板上的一对串行传输线，串联传输线与输入线的一端分离并分离并与之电磁连接; 分别在输入线和串行传输线的两侧形成在电介质基板上的一对平行传输线，并且其两端与输入线和串行传输线的一端分开并与之并联电磁连接 ; 以及电连接在并行传输线的另一端之间的一对电线和单片微波集成电路（MMIC）的连接焊盘。可以有效地传送从单片微波集成电路（MMIC）产生的约57至63GHz的电信号。

60. 发明申请

US20090261481A1 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译： WAFER LEVEL PACKAGE及其制作方法
公开(公告)号：US20090261481A1
公开(公告)日：2009-10-22
申请号：US12208512
申请日：2008-09-11
申请人： Jong Tae MOON , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
发明人： Jong Tae MOON , Yong Sung Eom , Min Ji Lee , Hyun Kyu Yu
IPC分类号： H01L23/52 , H01L21/66 , H01L21/00
CPC分类号： H01L23/10 , B81B7/007 , B81C2203/0118 , H01L24/45 , H01L24/48 , H01L24/94 , H01L2224/16145 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1461 , H01L2924/16235 , H01L2924/00 , H01L2924/2076 , H01L2224/05599
摘要： Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.
摘要翻译：提供了一种晶片级封装，其中可以容易地在内部器件和封装外部之间形成通信线，以及制造晶片级封装的方法。晶片级封装包括具有第一内部器件的空腔的第一衬底，形成在第一衬底上并与第一内部器件电连接的输入/输出（I / O）焊盘，设置在第一衬底上的第二衬底第一衬底并且从其中除去对应于I / O焊盘的部分，以及焊接第一和第二衬底的焊料。根据晶片级封装及其制造方法，上下基板被切割成不同的切割宽度，或者在上基板上形成孔，使得可以容易地形成内部装置的连通线，而不需要穿过基底的过程。因此，与使用通孔工艺制造的常规晶片级封装相比，可以简化制造工艺并降低生产成本。

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