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51. 发明申请

US20120028052A1 GRAPHENE GROWTH ON A NON-HEXAGONAL LATTICE 有权
公开(公告)号：US20120028052A1
公开(公告)日：2012-02-02
申请号：US12844029
申请日：2010-07-27
申请人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
发明人： Jack O. Chu , Christos Dimitrakopoulos , Marcus O. Freitag , Alfred Grill , Timothy J. McArdle , Chun-Yung Sung , Robert L. Wisnieff
IPC分类号： B32B17/06 , H01L21/20
CPC分类号： H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/188 , H01L21/02378 , H01L21/02433 , H01L21/02447 , H01L21/02516 , Y10T428/30
摘要： A graphene layer is formed on a crystallographic surface having a non-hexagonal symmetry. The crystallographic surface can be a surface of a single crystalline semiconductor carbide layer. The non-hexagonal symmetry surface of the single crystalline semiconductor carbide layer is annealed at an elevated temperature in ultra-high vacuum environment to form the graphene layer. During the anneal, the semiconductor atoms on the non-hexagonal surface of the single crystalline semiconductor carbide layer are evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed, the carbon concentration on the surface of the semiconductor-carbon alloy layer increases. Despite the non-hexagonal symmetry of the surface of the semiconductor-carbon alloy layer, the remaining carbon atoms can coalesce to form a graphene layer having hexagonal symmetry.

52. 发明申请

US20110086473A1 HYBRID ORIENTATION SEMICONDUCTOR STRUCTURE WITH REDUCED BOUNDARY DEFECTS AND METHOD OF FORMING SAME 有权
标题翻译：具有减少边界缺陷的混合方向半导体结构及其形成方法
公开(公告)号：US20110086473A1
公开(公告)日：2011-04-14
申请号：US12972771
申请日：2010-12-20
申请人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
发明人： Haizhou Yin , John A. Ott , Katherine L. Saenger , Chun-Yung Sung
IPC分类号： H01L21/8238 , H01L21/265
CPC分类号： H01L21/02694 , H01L21/02532 , H01L21/76264 , Y10S438/973
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for forming hybrid orientation substrates and semiconductor device structures. A direct-silicon-bonded (DSB) silicon layer having a (011) surface crystal orientation is bonded to a base silicon substrate having a (001) surface crystal orientation to form a DSB wafer in which the in-plane direction of the (011) DSB layer is aligned with an in-plane direction of the (001) base substrate. Selected regions of the DSB layer are amorphized down to the base substrate to form amorphized regions aligned with the mutually orthogonal in-plane directions of the (001) base substrate, followed by recrystallization using the base substrate as a template. This optimal arrangement of DSB layer, base substrate, and amorphized region orientation provides a near-vertical, essentially defect-free boundary between original-orientation and changed-orientation silicon regions, thus enabling complete boundary region removal with smaller footprint shallow trench isolation than possible with ATR methods not so optimized.
摘要翻译：本发明提供用于形成混合取向基板和半导体器件结构的改进的非晶化/模板重结晶（ATR）方法。具有（011）表面晶体取向的直接硅键合（DSB）硅层被结合到具有（001）表面晶体取向的基底硅基板上，以形成其中面内<110>方向的DSB晶片（011）DSB层与（001）基底的面内<110>方向对准。 DSB层的选定区域被非晶化到底部基板以形成与（001）基底基板的相互正交的平面内100°方向对准的非晶形区域，然后使用基底基板作为模板进行重结晶。 DSB层，基底和非晶区域取向的这种最佳布置提供了原始取向和改变取向硅区域之间近似垂直的，基本上无缺陷的边界，因此可以实现完整的边界区域移除，并且可以实现更小的占地面积的浅沟槽隔离 ATR方法没有如此优化。

53. 发明授权

US07618857B2 Method of reducing detrimental STI-induced stress in MOSFET channels 有权
标题翻译：降低MOSFET通道中有害的STI诱发应力的方法
公开(公告)号：US07618857B2
公开(公告)日：2009-11-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

54. 发明申请

US20080248626A1 SHALLOW TRENCH ISOLATION SELF-ALIGNED TO TEMPLATED RECRYSTALLIZATION BOUNDARY 审中-公开
标题翻译： SHOWOW TRENCH ISOLATION自对准至模拟重构边界
公开(公告)号：US20080248626A1
公开(公告)日：2008-10-09
申请号：US11697102
申请日：2007-04-05
申请人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
发明人： Yaocheng Liu , Zhijiong Luo , Katherine L. Saenger , Chun-Yung Sung , Rajasekhar Venigalla , Haizhou Yin
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , H01L21/02667 , H01L21/187 , H01L21/76224
摘要： A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.
摘要翻译：通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB）顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

55. 发明申请

US20080108204A1 AMORPHIZATION/TEMPLATED RECRYSTALLIZATION METHOD FOR HYBRID ORIENTATION SUBSTRATES 失效
标题翻译：用于混合定向衬底的拟合/调制再结晶方法
公开(公告)号：US20080108204A1
公开(公告)日：2008-05-08
申请号：US11871694
申请日：2007-10-12
申请人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/76
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽界定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 未被沟槽限定的非ATR区域的去除退火。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

56. 发明申请

US20070187670A1 Opto-thermal annealing mask and method 失效
标题翻译：光热退火掩模和方法
公开(公告)号：US20070187670A1
公开(公告)日：2007-08-16
申请号：US11355799
申请日：2006-02-16
申请人： Louis Hsu , Jack Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
发明人： Louis Hsu , Jack Mandelman , Chandrasekhar Narayan , Chun-Yung Sung
IPC分类号： H01L29/06
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译：光热退火掩模层叠层包括位于衬底上的散热层。反射层位于热耗散层上。可以具有约10至约100埃厚度的透明覆盖层位于反射层上。光热退火掩模层可以用作场效应器件中的栅电极。

57. 发明申请

US20070018239A1 Sea-of-fins structure on a semiconductor substrate and method of fabrication 审中-公开
标题翻译：半导体衬底上的海鳍结构和制造方法
公开(公告)号：US20070018239A1
公开(公告)日：2007-01-25
申请号：US11185646
申请日：2005-07-20
申请人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
发明人： Howard Chen , Louis Hsu , Jack Mandelman , Chun-Yung Sung
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L27/1211 , H01L29/66795 , H01L29/66803 , H01L29/785 , Y10S977/734 , Y10S977/742 , Y10S977/749 , Y10S977/815 , Y10S977/955
摘要： A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is adapted to be used in customized applications as a customized semiconductor device.
摘要翻译：一种半导体器件和半导体器件的制造方法，其中所述方法包括在衬底上形成多个用于定制鳍状场效应晶体管（FinFET）器件形成的平坦化翅片体; 在所述多个翅片体中的每一个周围形成氮化物间隔物; 在每个翅片体之间形成隔离区域; 并用保护膜涂覆多个翅片体，氮化物间隔物和隔离区域。制造的半导体器件适用于定制应用中作为定制的半导体器件。

58. 发明申请

US20060276011A1 Amorphization/templated recrystallization method for hybrid orientation substrates 失效
标题翻译：混合取向基板的非晶化/模板重结晶方法
公开(公告)号：US20060276011A1
公开(公告)日：2006-12-07
申请号：US11142646
申请日：2005-06-01
申请人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
发明人： Keith Fogel , Katherine Saenger , Chun-Yung Sung , Haizhou Yin
IPC分类号： H01L21/36
CPC分类号： H01L21/02675 , H01L21/02532 , H01L21/2022 , H01L21/76224 , H01L21/823807
摘要： The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.
摘要翻译：本发明提供了用于制造低缺陷密度混合取向基材的改进的非晶化/模板重结晶（ATR）方法。用于混合取向衬底制造的ATR方法通常从具有第一取向键合到具有第二取向的第二Si层或衬底的Si层开始。第一Si层的选定区域是非晶化的，然后通过使用第二Si层作为模板将其再结晶成第二Si层的取向。本发明的工艺流程解决了现有技术ATR方法未公开的两个主要困难：在由沟槽限定的非晶化Si区域的边缘产生“角部缺陷”，以及在高温后再结晶缺陷 - 非ATR区域的去除退火不受沟槽限制。特别地，本发明提供了一种工艺流程，其包括以下步骤：（i）在没有沟槽的衬底区域中进行非晶化和低温重结晶，（ii）形成在ATR'边缘处的缺陷区域的沟槽隔离区域的形成， d区域，以及（iii）在沟槽隔离区域中进行的高温缺陷去除退火。

59. 发明申请

US20060148215A1 METHOD OF FABRICATING A FIELD EFFECT TRANSISTOR HAVING IMPROVED JUNCTIONS 失效
标题翻译：制作具有改进的结的场效应晶体管的方法
公开(公告)号：US20060148215A1
公开(公告)日：2006-07-06
申请号：US10905454
申请日：2005-01-05
申请人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
发明人： Huilong Zhu , Oleg Gluschenkov , Chun-Yung Sung
IPC分类号： H01L21/20 , H01L21/425
CPC分类号： H01L21/26506 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.
摘要翻译：提供一种形成场效应晶体管的方法，其包括从单晶半导体区域形成具有第一深度的非晶化半导体区域，随后在非晶化半导体区域的沟道部分的上方形成第一栅极导体。然后将包括n型掺杂剂和p型掺杂剂中的至少一种的第一掺杂剂注入第二深度到不被第一栅极导体掩蔽的非晶化半导体区域的部分，以形成邻近沟道的源极/漏极部分一部分。然后将衬底加热以使非晶化半导体区域的沟道部分和源极/漏极部分重结晶。在加热步骤之后，至少部分重结晶的半导体区域被局部加热以在沟道部分和源极/漏极部分中的至少一个中激活掺杂剂。

60. 发明申请

US20060014356A1 Metal-insulator-metal capacitor and method of fabricating same 有权
标题翻译：金属绝缘体金属电容器及其制造方法
公开(公告)号：US20060014356A1
公开(公告)日：2006-01-19
申请号：US11205719
申请日：2005-08-17
申请人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
发明人： Louis Hsu , Rajiv Joshi , Chun-Yung Sung
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01G4/228 , H01G4/33 , H01L21/768 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings. MIM capacitors and methods of fabricating same are described, wherein the MIM capacitors are formed simultaneously with the BEOL interconnect and large density MIM capacitors are fabricated at low cost.
摘要翻译：一种金属绝缘体金属（MIM）电容器，包括金属层，形成在金属层上的绝缘层，至少第一开口和形成在第一绝缘层中的至少第二开口，形成在第一开口中的电介质层沉积在第一和第二开口中的导电材料和形成在第一开口上的第一金属板和形成在第二开口上的第二金属板。一种制造MIM电容器的方法，包括形成第一金属层，在第一金属层上形成绝缘层，至少在第一绝缘层中形成第一开口和至少第二开口，在第二开口上沉积掩模在第一开口中形成电介质层，去除掩模，在第一和第二开口中沉积导电材料，并在第一和第二开口上沉积第二金属层。描述MIM电容器及其制造方法，其中MIM电容器与BEOL互连同时形成，并且以低成本制造大密度MIM电容器。

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