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51. 发明申请

US20110219187A1 CACHE DIRECTORY LOOKUP READER SET ENCODING FOR PARTIAL CACHE LINE SPECULATION SUPPORT 有权
标题翻译： CACHE DIRECTORY LOOKUP READER SET ENCODING FOR CLASS CACHE LINE SPECTRATION SUPPORT
公开(公告)号：US20110219187A1
公开(公告)日：2011-09-08
申请号：US13008602
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, with conflict checking implemented in a directory lookup of a shared cache memory, a reader set encoding permits dynamic recordation of read accesses. The reader set encoding includes an indication of a portion of a line read, for instance by indicating boundaries of read accesses. Different encodings may apply to different types of speculative execution.
摘要翻译：在多处理器系统中，通过在共享高速缓冲存储器的目录查找中实现冲突检查，读取器集合编码允许读取访问的动态记录。读取器组编码包括例如通过指示读取访问的边界来读取行的一部分的指示。不同的编码可能适用于不同类型的投机执行。

52. 发明申请

US20110173394A1 ORDERING OF GUARDED AND UNGUARDED STORES FOR NO-SYNC I/O 失效
标题翻译：订购非同步I / O的保护和无保留存储
公开(公告)号：US20110173394A1
公开(公告)日：2011-07-14
申请号：US12986349
申请日：2011-01-07
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F12/0808
摘要： A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
摘要翻译：并行计算系统处理至少一个存储指令。第一个处理器核心发出存储指令。与第一处理器核心相关联的第一个队列存储存储指令。与第一处理器核心的第一本地高速缓冲存储器设备相关联的第二队列存储存储指令。第一处理器核心根据存储指令来更新第一本地高速缓冲存储器设备中的第一数据。与至少一个共享高速缓冲存储器设备相关联的第三队列存储存储指令。第一处理器核心使与存储指令相关联的第二数据在至少一个共享高速缓冲存储器中无效。第一个处理器核心将与存储指令相关联的第三个数据与其他处理器内核的其他本地缓存存储器设备无效。第一个处理器核心只冲刷第一个队列。

53. 发明申请

US20110047334A1 Checkpointing in Speculative Versioning Caches 失效
标题翻译：推测版本控制缓存中的检查点
公开(公告)号：US20110047334A1
公开(公告)日：2011-02-24
申请号：US12544704
申请日：2009-08-20
申请人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
发明人： Alexandre E. Eichenberger , Alan Gara , Michael K. Gschwind , Martin Ohmacht
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F11/1405
摘要： Mechanisms for generating checkpoints in a speculative versioning cache of a data processing system are provided. The mechanisms execute code within the data processing system, wherein the code accesses cache lines in the speculative versioning cache. The mechanisms further determine whether a first condition occurs indicating a need to generate a checkpoint in the speculative versioning cache. The checkpoint is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint in the speculative versioning cache in response to a determination that the first condition has occurred.
摘要翻译：提供了用于在数据处理系统的推测版本缓存中生成检查点的机制。这些机制在数据处理系统内执行代码，其中代码访问推测版本控制缓存中的高速缓存行。这些机制进一步确定是否出现指示在推测版本控制高速缓存中生成检查点的需要的第一条件。检查点是推测性高速缓存行，其响应于需要向对应于推测性高速缓存行的高速缓存行的回滚而返回的第二条件而变得不推测。这些机制还响应于确定第一个条件已经发生，在推测版本控制缓存中生成检查点。

54. 发明授权

US08868837B2 Cache directory lookup reader set encoding for partial cache line speculation support 有权
标题翻译：缓存目录查找阅读器集编码为部分缓存线投机支持
公开(公告)号：US08868837B2
公开(公告)日：2014-10-21
申请号：US13008602
申请日：2011-01-18
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a multiprocessor system, with conflict checking implemented in a directory lookup of a shared cache memory, a reader set encoding permits dynamic recordation of read accesses. The reader set encoding includes an indication of a portion of a line read, for instance by indicating boundaries of read accesses. Different encodings may apply to different types of speculative execution.
摘要翻译：在多处理器系统中，通过在共享高速缓冲存储器的目录查找中实现冲突检查，读取器集合编码允许读取访问的动态记录。读取器组编码包括例如通过指示读取访问的边界来读取行的一部分的指示。不同的编码可能适用于不同类型的投机执行。

55. 发明授权

US08473683B2 Ordering of guarded and unguarded stores for no-sync I/O 失效
标题翻译：为不同步I / O订购防护和无保护的存储
公开(公告)号：US08473683B2
公开(公告)日：2013-06-25
申请号：US12986349
申请日：2011-01-07
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F12/12
CPC分类号： G06F12/0811 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F12/0808
摘要： A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
摘要翻译：并行计算系统处理至少一个存储指令。第一个处理器核心发出存储指令。与第一处理器核心相关联的第一个队列存储存储指令。与第一处理器核心的第一本地高速缓冲存储器设备相关联的第二队列存储存储指令。第一处理器核心根据存储指令来更新第一本地高速缓冲存储器设备中的第一数据。与至少一个共享高速缓冲存储器设备相关联的第三队列存储存储指令。第一处理器核心使与存储指令相关联的第二数据在至少一个共享高速缓冲存储器中无效。第一个处理器核心将与存储指令相关联的第三个数据与其他处理器内核的其他本地缓存存储器设备无效。第一个处理器核心只冲刷第一个队列。

56. 发明申请

US20110219191A1 READER SET ENCODING FOR DIRECTORY OF SHARED CACHE MEMORY IN MULTIPROCESSOR SYSTEM 失效
标题翻译：在多处理器系统中编写共享高速缓存存储器的目录的读写器集
公开(公告)号：US20110219191A1
公开(公告)日：2011-09-08
申请号：US13008583
申请日：2011-01-18
申请人： Daniel Ahn , Luis H. Ceze , Alan Gara , Martin Ohmacht , Zhuang Xiaotong
发明人： Daniel Ahn , Luis H. Ceze , Alan Gara , Martin Ohmacht , Zhuang Xiaotong
IPC分类号： G06F12/08
CPC分类号： G06F9/524 , G06F12/08
摘要： In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.
摘要翻译：在具有推测性执行的并行处理系统中，冲突检查发生在所有处理器共享的高速缓冲存储器的目录查找中。在每种情况下，相同的物理内存地址将映射到同一组缓存，无论哪个处理器发起该访问。该目录包括一个动态阅读器集编码，指示什么推测线程读取了一条特定的行。这种读写器编码用于冲突检查。位组编码用于指定已读取行的特定线程。

57. 发明申请

US20060230239A1 Method and apparatus for detecting a cache wrap condition 有权
标题翻译：用于检测缓存包装条件的方法和装置
公开(公告)号：US20060230239A1
公开(公告)日：2006-10-12
申请号：US11093132
申请日：2005-03-29
申请人： Matthias Blumrich , Alan Gara , Mark Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias Blumrich , Alan Gara , Mark Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

58. 发明申请

US20120331232A1 WRITE-THROUGH CACHE OPTIMIZED FOR DEPENDENCE-FREE PARALLEL REGIONS 有权
标题翻译：写入 - 通过高速缓存优化为无依赖的并行区域
公开(公告)号：US20120331232A1
公开(公告)日：2012-12-27
申请号：US13604349
申请日：2012-09-05
申请人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
发明人： Alexandre E. Eichenberger , Alan Gara , Martin Ohmacht , Vijayalakshmi Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F12/0837
摘要： An apparatus and computer program product for improving performance of a parallel computing system. A first hardware local cache controller associated with a first local cache memory device of a first processor detects an occurrence of a false sharing of a first cache line by a second processor running the program code and allows the false sharing of the first cache line by the second processor. The false sharing of the first cache line occurs upon updating a first portion of the first cache line in the first local cache memory device by the first hardware local cache controller and subsequent updating a second portion of the first cache line in a second local cache memory device by a second hardware local cache controller.
摘要翻译：一种用于提高并行计算系统性能的设备和计算机程序产品。与第一处理器的第一本地高速缓冲存储器设备相关联的第一硬件本地高速缓存控制器通过运行程序代码的第二处理器来检测第一高速缓存行的虚假共享的发生，并允许第一高速缓存行的错误共享由第二处理器。当由第一硬件本地高速缓存控制器更新第一本地高速缓存存储器设备中的第一高速缓存行的第一部分并且随后在第二本地高速缓冲存储器中更新第一高速缓存行的第二部分时，发生第一高速缓存行的错误共享设备由第二硬件本地缓存控制器。

59. 发明申请

US20110047362A1 Version Pressure Feedback Mechanisms for Speculative Versioning Caches 失效
标题翻译：版本控制缓存的版本压力反馈机制
公开(公告)号：US20110047362A1
公开(公告)日：2011-02-24
申请号：US12543688
申请日：2009-08-19
申请人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , Alan Gara , Kathryn M. O'Brien , Martin Ohmacht , Xiaotong Zhuang
IPC分类号： G06F12/08 , G06F9/318
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/0842
摘要： Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache.
摘要翻译：提供了用于控制推测版本缓存的版本压力的机制。基于访问推测性版本缓存的高速缓存行的一个或多个线程来收集原始版本压力数据。基于收集的原始版本压力数据生成版本压力的一个或多个统计度量。确定是否将基于版本压力的一个或多个统计测量来执行对数据处理系统的操作的一个或多个修改，该一个或多个修改影响施加在推测版本缓存上的版本压力。响应于将要执行对数据处理系统的操作的一个或多个修改以影响施加在投机上的版本压力的确定，基于一个或多个确定的修改来修改数据处理系统的操作版本缓存。

60. 发明授权

US08838906B2 Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution 有权
标题翻译：在具有推测性执行的多处理器系统中写入时，预取单元和/或第一级缓存的管理策略
公开(公告)号：US08838906B2
公开(公告)日：2014-09-16
申请号：US12984308
申请日：2011-01-04
申请人： Alan Gara , Martin Ohmacht
发明人： Alan Gara , Martin Ohmacht
IPC分类号： G06F13/00
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F12/0804 , G06F12/0811 , G06F12/0897 , G06F2212/452 , G06F2212/507 , G06F2212/602 , Y02D10/13
摘要： In a multiprocessor system with at least two levels of cache, a speculative thread may run on a core processor in parallel with other threads. When the thread seeks to do a write to main memory, this access is to be written through the first level cache to the second level cache. After the write though, the corresponding line is deleted from the first level cache and/or prefetch unit, so that any further accesses to the same location in main memory have to be retrieved from the second level cache. The second level cache keeps track of multiple versions of data, where more than one speculative thread is running in parallel, while the first level cache does not have any of the versions during speculation. A switch allows choosing between modes of operation of a speculation blind first level cache.
摘要翻译：在具有至少两级高速缓存的多处理器系统中，推测线程可以与其他线程并行运行在核心处理器上。当线程寻求对主存储器进行写操作时，该访问将通过第一级缓存写入第二级缓存。在写入之后，从第一级高速缓存和/或预取单元删除相应的行，使得必须从第二级高速缓存检索对主存储器中相同位置的任何进一步访问。第二级缓存跟踪多个版本的数据，其中多个推测线程并行运行，而第一级缓存在推测期间没有任何版本。开关允许在推测盲目一级缓存的操作模式之间进行选择。

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