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51. 发明申请

US20090309688A1 Circuit apparatus and method of manufacturing the same 审中-公开
标题翻译：电路装置及其制造方法
公开(公告)号：US20090309688A1
公开(公告)日：2009-12-17
申请号：US12453512
申请日：2009-05-13
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01F5/00 , H01F41/04
CPC分类号： H01L23/48 , H01F17/0006 , H01F17/0013 , H01F41/041 , H01F41/10 , H01F2017/0046 , H01L23/49816 , H01L23/49822 , H01L23/5227 , H01L23/645 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0655 , H01L25/0657 , H01L28/10 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/45139 , H01L2224/48091 , H01L2224/4813 , H01L2224/48195 , H01L2224/48227 , H01L2224/48247 , H01L2224/484 , H01L2224/4918 , H01L2224/73204 , H01L2224/73265 , H01L2225/06517 , H01L2225/06527 , H01L2225/06572 , H01L2924/00011 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/12041 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , Y10T29/4902 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2924/01049
摘要： A circuit apparatus includes a first insulating layer, a first inductor, a first terminal, a second terminal, a first interconnect, and a wire. The first inductor is located at one surface of the first insulating layer and configured by a spiral conductive pattern. The first terminal and the second terminal are exposed from one surface of the first insulating layer. The first interconnect is formed on one surface of the first insulating layer to connect the first terminal and an external end of the first inductor. The wire is located on a one-surface side of the first insulating layer to connect the second terminal and a central end of the first inductor.
摘要翻译：电路装置包括第一绝缘层，第一电感器，第一端子，第二端子，第一互连件和导线。第一电感器位于第一绝缘层的一个表面，并由螺旋导电图案构成。第一端子和第二端子从第一绝缘层的一个表面露出。第一互连形成在第一绝缘层的一个表面上，以连接第一电感器的第一端子和外端。导线位于第一绝缘层的单面侧，以连接第二端子和第一电感器的中心端。

52. 发明申请

US20090283895A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090283895A1
公开(公告)日：2009-11-19
申请号：US12446899
申请日：2007-10-09
申请人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Katsumi Maeda , Takuo Funaya , Kentaro Mori , Takehiko Maeda , Masaya Kawano , Yuuji Kayashima
发明人： Katsumi Kikuchi , Shintaro Yamamichi , Hideya Murai , Katsumi Maeda , Takuo Funaya , Kentaro Mori , Takehiko Maeda , Masaya Kawano , Yuuji Kayashima
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L23/5389 , H01L24/19 , H01L2223/54486 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/92 , H01L2224/92244 , H01L2924/01012 , H01L2924/01015 , H01L2924/0102 , H01L2924/01027 , H01L2924/01029 , H01L2924/0104 , H01L2924/01042 , H01L2924/01046 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/83 , H01L2224/82
摘要： A semiconductor device including a metal frame having a penetrating opening; a semiconductor chip provided in the opening; an insulating layer provided on the upper surface of the metal frame such that the insulating layer covers the upper surface, which is the circuit-formed surface of the semiconductor chip; an interconnect layer provided only on the upper-surface side of the metal frame with intervention of the insulating material and electrically connected to a circuit of the semiconductor chip; a via conductor provided on the upper surface of said semiconductor chip to electrically connect the circuit of the semiconductor chip and the interconnect layer; and a resin layer provided on the lower surface of the metal frame.
摘要翻译：一种半导体器件，包括具有穿透开口的金属框架; 设置在开口内的半导体芯片; 绝缘层，设置在金属框架的上表面上，使得绝缘层覆盖作为半导体芯片的电路形成表面的上表面; 互连层，其仅在金属框架的上表面侧设置，并且绝缘材料的介入并且电连接到半导体芯片的电路; 设置在所述半导体芯片的上表面上的通孔导体，以电连接半导体芯片的电路和互连层; 以及设置在金属框架的下表面上的树脂层。

53. 发明申请

US20070235885A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070235885A1
公开(公告)日：2007-10-11
申请号：US11762793
申请日：2007-06-14
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L23/488
CPC分类号： H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2224/05099
摘要： A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed. a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.
摘要翻译：一种半导体器件，其以逻辑芯片的焊盘部分连接到具有凸块焊接的半导体芯片的元件区域的方式构成，因此能够实现元件的高速可操作性，因为延迟传输电信号被抑制。逻辑芯片直接连接到DRAM，因此，可以抑制由互连引起的负载电容的增加，并且通过多引脚连接来确保宽的总线宽度。结果，在抑制从逻辑芯片到DRAM的信息传输的延迟的情况下，可以提高半导体器件的性能。

54. 发明授权

US07247935B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07247935B2
公开(公告)日：2007-07-24
申请号：US11083983
申请日：2005-03-21
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13025 , H01L2224/16145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H01L2224/05099
摘要： A semiconductor device, which is constituted in such a way that a pad portion of a logic chip is connected to an element region of a semiconductor chip with a bump bonding, is capable of achieving high speed operability of the elements, because delay of transmission of an electrical signal is suppressed a logic chip is directly connected to a DRAM, therefore, it is possible to suppress an increase of load capacitance caused by interconnects, and securing a wide bus width by a multiple pin connection. As a result, it becomes possible to enhance performance of the semiconductor device upon suppressing delay of information transmission from the logic chip to the DRAM.
摘要翻译：一种半导体器件，其以逻辑芯片的焊盘部分连接到具有凸块焊接的半导体芯片的元件区域的方式构成，因此能够实现元件的高速可操作性，因为延迟传输电信号被抑制，逻辑芯片直接连接到DRAM，因此，可以抑制由互连引起的负载电容的增加，并且通过多引脚连接来确保宽的总线宽度。结果，在抑制从逻辑芯片到DRAM的信息传输的延迟的情况下，可以提高半导体器件的性能。

55. 发明申请

US20050121802A1 Offset-bonded, multi-chip semiconductor device 失效
标题翻译：偏移式多芯片半导体器件
公开(公告)号：US20050121802A1
公开(公告)日：2005-06-09
申请号：US10995491
申请日：2004-11-24
申请人： Masaya Kawano , Satoshi Matsui
发明人： Masaya Kawano , Satoshi Matsui
IPC分类号： H01L25/18 , H01L23/50 , H01L25/00 , H01L25/065 , H01L25/07 , H01L29/40
CPC分类号： H01L24/73 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2225/0651 , H01L2225/06513 , H01L2225/06555 , H01L2225/06562 , H01L2225/06593 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.
摘要翻译：本发明的目的在于通过将上芯片与下芯片相抵消，以高可靠性的方式将下芯片和上芯片焊接在一起，同时确保足够的外部连接端子区域。基板2在其一个表面上具有凸块1，并且具有安装在其另一个表面上的第一芯片3。第二芯片4通过凸块5,6接合到第一芯片3，同时平行地将第二芯片4与第一芯片3抵消。在第一芯片3和第二芯片4的接合状态下，第一芯片3的一部分和第二芯片4的一部分重叠而不对准两者的中心。第二芯片4的重心落在由第一芯片3和第二芯片4之间的最外侧的凸块包围的区域内。

56. 发明申请

US20050095845A1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050095845A1
公开(公告)日：2005-05-05
申请号：US10999003
申请日：2004-11-30
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76877 , H01L21/76838
摘要： A method of fabricating a semiconductor device, including at least the steps of (a) forming a via-hole or trench throughout an electrically insulating layer, (b) forming a wiring material layer on the electrically insulating layer such that the via-hole or trench is filled with the wiring material layer, (c) annealing the wiring material layer, (d) cooling the wiring material layer down to a temperature equal to or lower than a predetermined temperature, and (e) applying chemical mechanical polishing (CMP) to the wiring material layer such that the wiring material layer exists only in the via-hole or trench. The step (c) is carried out prior to the step (e), and the step (d) is carried out after the step (c).
摘要翻译：一种制造半导体器件的方法，至少包括（a）在整个电绝缘层中形成通孔或沟槽的步骤，（b）在电绝缘层上形成布线材料层，使得通孔或沟槽填充有布线材料层，（c）使布线材料层退火，（d）将布线材料层冷却至等于或低于预定温度的温度，和（e）施加化学机械抛光（CMP）到布线材料层，使得布线材料层仅存在于通孔或沟槽中。步骤（c）在步骤（e）之前进行，步骤（d）在步骤（c）之后进行。

57. 发明授权

US5581117A Si base substrate covered by a CdTe or Cd-rich CdZnTe layer 失效
标题翻译： Si基底由CdTe或Cd富集的CdZnTe层覆盖
公开(公告)号：US5581117A
公开(公告)日：1996-12-03
申请号：US571414
申请日：1995-12-13
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L21/205 , C30B23/02 , H01L21/20 , H01L21/203 , H01L21/36 , H01L21/363 , H01L31/0264 , H01L31/18 , H01L31/09 , H01L29/161 , H01L27/14 , H01L31/00
CPC分类号： H01L31/1836 , C30B23/02 , C30B29/48 , H01L21/02381 , H01L21/02433 , H01L21/0248 , H01L21/02502 , H01L21/02562 , H01L21/02568 , H01L21/02609 , H01L21/0262 , Y02E10/50
摘要： The present invention provides an Si base semiconductor monocrystal substrate which includes an Si(11n) substrate where n=1.5-2.5. An intermediate layer is formed on the Si(11n) substrate. The intermediate layer is made of a material selected from the group consisting of ZnTe and Zn-rich CdZnTe, The intermediate layer has a thickness in the range of 50-200 angstroms. The intermediate layer is oriented in a (11n')B plane. An upper layer is formed on the intermediate layer. The upper layer is made of a material selected from the group consisting of CdTe and Cd-rich CdZnTe. The upper layer is oriented in a (11n")B plane. The indexes n' and n" satisfy the following equations. ##EQU1## where y is the lattice mismatch between the Si substrate and the intermediate layer. ##EQU2## where y' is the lattice mismatch between the Si substrate and the upper layer.
摘要翻译：本发明提供一种Si基半导体单晶衬底，其包括n = 1.5-2.5的Si（11n）衬底。在Si（11n）衬底上形成中间层。中间层由选自ZnTe和富Zn的CdZnTe的材料制成，中间层的厚度在50-200埃的范围内。中间层定向为（11n'）B平面。在中间层上形成上层。上层由选自CdTe和Cd的CdZnTe的材料制成。上层定向为（11n“）B平面。索引n'和n“满足下列等式。其中y是Si衬底和中间层之间的晶格失配。其中y'是Si衬底和上层之间的晶格失配。

58. 发明授权

US08975150B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08975150B2
公开(公告)日：2015-03-10
申请号：US13190052
申请日：2011-07-25
申请人： Kentaro Mori , Shintaro Yamamichi , Hideya Murai , Takuo Funaya , Masaya Kawano , Takehiko Maeda , Kouji Soejima
发明人： Kentaro Mori , Shintaro Yamamichi , Hideya Murai , Takuo Funaya , Masaya Kawano , Takehiko Maeda , Kouji Soejima
IPC分类号： H01L21/76 , H01L21/683 , H01L23/538 , H01L23/544 , H01L23/00
CPC分类号： H01L21/6835 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L24/24 , H01L2221/68345 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01057 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/15174 , H01L2924/15788 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3011 , Y10S438/977 , H01L2924/00
摘要： A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.
摘要翻译：透明板位于设置有定位标记的支撑板上，并且设置有释放材料。然后将半导体元件定位成使得电极元件面向上，然后移除支撑板。然后在剥离材料上形成绝缘树脂以覆盖半导体元件; 然后形成通孔，布线层，绝缘层，外部端子和阻焊剂。然后透明板通过使用释放材料从半导体器件剥离。因此，可以高精度地安装芯片，在制造过程中不需要在将芯片安装在基板上时提供定位标记，并且可以容易地去除基板。结果，可以以低成本制造具有高密度和薄型的半导体器件。

59. 发明授权

US08072073B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08072073B2
公开(公告)日：2011-12-06
申请号：US12210702
申请日：2008-09-15
申请人： Katsumi Kikuchi , Shintaro Yamamichi , Masaya Kawano , Kouji Soejima
发明人： Katsumi Kikuchi , Shintaro Yamamichi , Masaya Kawano , Kouji Soejima
IPC分类号： H01L29/40 , H01L21/44
CPC分类号： H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L24/05 , H01L2924/00013 , H01L2924/01019 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2224/29099 , H01L2924/00
摘要： A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate; a first wiring structure placed on the semiconductor substrate and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure placed on the first wiring structure and having one or more second wiring layers, one or more second insulating layers, a second via and a third via; and an external terminal provided on the second wiring structure. The second via, which is connected to the second wiring layer of the second wiring structure and to the external terminal, has a connection interface disposed at an end of the via that is on the side of the external terminal.
摘要翻译：在非常小的通孔中确保连接可靠性的高度可靠的半导体器件包括：半导体衬底; 放置在半导体衬底上并具有一个或多个第一布线层，一个或多个绝缘层和第一通孔的第一布线结构; 放置在第一布线结构上并具有一个或多个第二布线层，一个或多个第二绝缘层，第二通孔和第三通孔的第二布线结构; 以及设置在第二布线结构上的外部端子。连接到第二布线结构的第二布线层和外部端子的第二通孔具有布置在位于外部端子一侧的通孔的端部处的连接接口。

60. 发明授权

US08008191B2 Semiconductor device and method for manufacturing the same 有权
公开(公告)号：US08008191B2
公开(公告)日：2011-08-30
申请号：US12427366
申请日：2009-04-21
申请人： Masaya Kawano
发明人： Masaya Kawano
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L2224/05001 , H01L2224/05009 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/10329 , H01L2924/13091 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

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