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51. 发明专利

JPS5724579A Infrared detector 失效
标题翻译：红外探测器
公开(公告)号：JPS5724579A
公开(公告)日：1982-02-09
申请号：JP10093880
申请日：1980-07-22
申请人： Mitsubishi Electric Corp
发明人： TSUBOUCHI NATSUO , UEMATSU SHIGEYUKI
IPC分类号： H01L31/108 , H01L31/024
CPC分类号： H01L31/024
摘要： PURPOSE:To obtain a sufficient cooling and a uniform cooling temperature in a silicon Shottky type infrared detector, by cooling directly the Shottky diode part through a resin having a good heat conductivity. CONSTITUTION:A silicon substrate 1 provided with a Shottky diode 2 for detecting infrared rays and bump 3 is connected to a mounting base board 4 through a resin 6 of good heat conductivity such as a silicon compound. Infrared rays 5 are applied to the second main surface of the substrate 1 of the infrared detector constructed as described above.
摘要翻译：目的：为了在硅肖特基型红外检测器中获得足够的冷却和均匀的冷却温度，通过具有良好导热性的树脂直接对肖特基二极管部件进行冷却。构成：设置有用于检测红外线和凸起3的肖特基二极管2的硅基板1通过具有良好导热性的树脂6（例如硅化合物）连接到安装基板4。红外线5被施加到如上所述构造的红外检测器的基板1的第二主表面上。

52. 发明专利

JPS56105652A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS56105652A
公开(公告)日：1981-08-22
申请号：JP897780
申请日：1980-01-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： DENDA MASAHIKO , SATOU SHINICHI , ITOU KAZUO , TSUBOUCHI NATSUO
IPC分类号： H01L21/76 , H01L21/265 , H01L21/316 , H01L21/762
摘要： PURPOSE:To separate elements from other elements in high precision without an appearance of defects by selectively injecting to a substrate the impurity ions which form an insulator under the reaction to Si at high temperature and treating the same at high temperature in an inactive gas. CONSTITUTION:An n type Si is applied with a resist mask 7 to form an O -ion injected layer 8. The resist film can be formed easier and in higher precision than Si3N4. Removal and treatment of the mask by O2 plasma at high temperature in N2 bring the O -ions in the reaction to Si to form an oxidized film 9, a lateral reaction by the external atmosphere not taking place, a strain seldom appearing except in the separated layer and no crystal defect being produced. According to conditions of the O-ion injection and of the heat treatment, the oxidized film 9 of Si2O3 and the like containing O in a low ratio after than SiO2 is produced as well. A p layer 4 is formed as the mask of the film 9 and a poly-Si electrode 6a is formed which extends over a part of the surface of SiO25 and the film 9. With this construction, the elements separated layer can easily be formed in high precision.

53. 发明专利

JPS5679433A FORMING OF ULTRA FINE PATTERN 失效
公开(公告)号：JPS5679433A
公开(公告)日：1981-06-30
申请号：JP15650579
申请日：1979-11-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , TSUBOUCHI NATSUO , NAGATOMO MASAO , HARADA HIROJI , MIHASHI JIYUNICHI
IPC分类号： H01L21/3213 , H01L21/302 , H01L21/3065
摘要： PURPOSE:To facilitate the forming of an ultra fine pattern by a method wherein Mo film is coated on a base layer when the ultra fine pattern electrode is formed on a semiconductor, antioxide film layer is made on the film in accordance with the pattern to be left, heat treated in an oxidation atmosphere to sublimate the Mo film in the exposed area. CONSTITUTION:Mo film layer 2 is coated on a surface of the base layer 1, anitoxide film 3 such as Al film, Si3N4 film SiO2 film etc. is arranged in accordance with the desired pattern, heat treated at a temperature higher than 400 deg.C in the atmosphere of O2 of which pressure is decreased or increased, and the Mo film 2 in the exposed area is changed to the film 4 such as MoO2, MoO3 etc. Similarly, the sublimation of the film 4 is used to sublimate the same to keep the Mo film 2 of ultra fine pattern only below the film 3. With this arrangement, regardless of the material quality of the base layer, a forming of the ultra fine pattern can be facilitated.

54. 发明专利

JPS5656641A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5656641A
公开(公告)日：1981-05-18
申请号：JP13390579
申请日：1979-10-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIYOSHI HIROKAZU , HARADA HIROJI , TSUBOUCHI NATSUO , WAKAMIYA WATARU , DENDA MASAHIKO , SATOU SHINICHI
IPC分类号： H01L21/768 , H01L21/316 , H01L21/60
摘要： PURPOSE:To obtain a smooth surface by a method wherein a polycrystalline Si film is laminated on a substrate having a difference in level according to depressurization CVD process, which is oxidized thermally to an oxidized film. CONSTITUTION:After providing field oxidized film 2, N type source, drain 5, gate oxidized film 6, polycrystalline Si gate electrode and wiring 4 and Si3N4 mask 7 on a P type Si substrate 1, P dropped polycrystalline Si 8 is formed by means of SiH4 and PH3 at 630 deg.C and 0.8torr of gas pressure according to depressurization CVD process. Next, the polycrystalline Si 8 is converted into SiO2 9 through high pressure oxidation at 850 deg.C and 5kg/cm in steam pressure. Then, an opening is provided in the SiO2 film 9 to expose Si3N4 film 7, the film 7 is removed through plasma etching, and an opening 10 is provided in the SiO2 film 6 witg HF aqueous solution. An Al wiring 11 is provided thereafter. According to this method, a difference in level is flattened at the gate electrode or the wiring 4 according to a cubical expansion at the time of conversion into the oxidized film 9, thus preventing disconnection. Moreover, an electrode window same in area can be formed for the presence of Si3N4 film, and a high pressure oxidation can be introduced to save a high temperature treatment.

55. 发明专利

JPS5654052A FORMATION OF MULTILAYER WIRING CONSTRUCTION 失效
公开(公告)号：JPS5654052A
公开(公告)日：1981-05-13
申请号：JP13037779
申请日：1979-10-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , HARADA HIROJI , MIYOSHI HIROKAZU , WAKAMIYA WATARU , DENDA MASAHIKO , SATOU SHINICHI
IPC分类号： H05K3/46 , H01L21/3205 , H01L21/768
摘要： PURPOSE:To obtain the multilayer wiring free from disconnection by stacking an amorphous Si layer including impurities on an Al or Al alloy layer, selectively oxidizing the layers with a mask and piling the Al or Al alloy layers together with the removal of the mask. CONSTITUTION:The amorphous Si 8 and Si3N4 9 are formed on Al 3 and 3' at a low temperature by plasma CVD method. A film 9 is selectively etched to make a mask 9' and Si 8 is oxidized at a temperature below the melting point of Al by plasma anode oxidiation method or the like to be converted into Si3N4 4'. With the removal of the mask 9', the second Al wiring layer is laminated thereon. As the amorphous Si 8 at the through hole part is connected to the Al layer to form a flat construction with no step, disconnection can be avoided at the part. The use of a phosphoric acid-based etching liquid after the etching of Al allows selective etching of Al layer 7 alone thereby improving the float level of the through hole part. The resistance value of the amorphous Si can be lowered by adding impurities thereto properly.

56. 发明专利

JPS5654049A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5654049A
公开(公告)日：1981-05-13
申请号：JP13038079
申请日：1979-10-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , YONEDA MASAHIRO , NAGASAWA KOUICHI , HARADA HIROJI , HIRATA KATSUHIRO , DENDA MASAHIKO
IPC分类号： H01L21/31 , H01L21/318 , H01L21/76 , H01L21/762
摘要： PURPOSE:To obtain a separation groove with a flat surface in a small area by stacking an Si3N4 film in a groove between circuit elements. CONSTITUTION:An N layer 2 is made on a P type substrate 1 and an N epitaxial layer 3 is grown thereon. With an SiO2 maks 4, a vertical separation groove is produced by reactive ion etching. Then, an SiO2 thin film 6 is formed on the inner surface of the groove by thermal oxidization while a channel cut is made onthe bottom with the implantation of B ion. An Si3N4 7 is formed from a gas mixture of SiH2Cl2, NH3 and N2 by decompression CVD method to bury the groove. As the film 7 is stacked through surface reaction, it grows faithful to the surface and buried almost flat to thereof. No flat surface can not be obtained by nromal pressure CVD method. Then, the Si3N4 film 7 is etched away until an SiO2 film 4 is exposed. Thereafter, the semiconductor is formed as in the past. With such an arrangement, a separation construction between elements is obtained with a flat surface in a small area. The quick low temperature formation thereof eliminates redistribution of the diffusion and induced lack of crystal.

57. 发明专利

JPS5654045A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5654045A
公开(公告)日：1981-05-13
申请号：JP13039379
申请日：1979-10-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： MIYOSHI HIROKAZU , SATOU SHINICHI , DENDA MASAHIKO , WAKAMIYA WATARU , NOMOTO SUMIO , TSUBOUCHI NATSUO
IPC分类号： H01L21/76 , H01L21/316 , H01L21/768
摘要： PURPOSE:To improve the reliability of an element by a method wherein a worked step part on an Si substrate is coated with poly Si or amorphous Si, P is further deposited, and the Si is oxidized and changed into an oxide film. CONSTITUTION:Poly Si 8 is laminated on an Si substrate 1, in which worked step part is formed by a gate electrode 4 and a wiring portion 5, by means of a CVD method, and P 9 is deposited. When oxidizing the poly Si film 8 under 5kg/cm steam pressure at about 850 deg.C, the film 8 is completely changed into an oxide film 10, and only the surface is softened and planed. Thereafter, an electrode is attached according to the fixed method. According to this method, the reliability of an element is improved different from conventional PSG coating methods because the P of high concentration does not hardly reach a surface of the substrate 1. When P is contained in the poly Si 8 at extremely low concentration, the poly Si film is easy to be melted and readily planed. Coating with an amorphous Si film is similarly effective.

58. 发明专利

JPS5651840A PREPARATION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5651840A
公开(公告)日：1981-05-09
申请号：JP12906279
申请日：1979-10-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： TSUBOUCHI NATSUO , SATOU SHINICHI , DENDA MASAHIKO
IPC分类号： H01L29/78 , H01L21/316 , H01L21/76 , H01L21/762
摘要： PURPOSE:To reduce the parasitic capacity of a semiconductor device and prevent the narrow channel effect by doping impurities of different conductivity type from a substrate into the active regions of the semiconductor substrate having a high impurity atom concentration in order to form a region having the same conductivity type as the substrate and a low impurity atom concentration. CONSTITUTION:Into the active regions for a source, drain, gate and wiring of a ptype semiconductor substrate 1 whose field region is coated with a thermal oxide film 3, phosphorous ions are implanted and treated with heat to diffuse the phosphorous ions. The substrate 1 is to have a high impurity atom concentration so that the threshold voltage of the substrate 1 under wiring is above the working voltage. Formed by this is a region 7 having a lower impurity atom concentration than the substrate 1 yet the type is p, and formed following this are a gate oxide film 5, gate electrode 6 and n type impurity regions 4 for drain, source and wiring. A MOSIC manufactured by such method has a small parasitic capacity because the junctions between the regions 4 and the substrate 1 are all in the region 7. Moreover, because there is no lateral diffusion in the field dope impurity layer, the narrow channel effect can be prevented.

59. 发明专利

JPS5645761A PLASMA REACTION APPARATUS 失效
公开(公告)号：JPS5645761A
公开(公告)日：1981-04-25
申请号：JP12337179
申请日：1979-09-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： ABE HARUHIKO , DENDA MASAHIKO , HIRATA KATSUHIRO , KINOSHITA SHIGEJI , TSUBOUCHI NATSUO , HARADA HIROTSUGU
IPC分类号： B01J19/08 , C23F4/00 , H01L21/30 , H01L21/302 , H01L21/3065 , H05H1/46
摘要： PURPOSE:To obtain a parallel flat plate electrode type plasma reaction apparatus capable of controlling a plasma condition by forming a stationary magnetic field to a direction parallel to a surface of a parallel flat plate electrode. CONSTITUTION:In a parallel flat plate electrode type plasma reaction apparatus, between an upper electrode 3 and a lower electrode 4, controlled stationary magnetic field generating coils 9a, 9b generating a stationary magnetic field parallel to a surface of the electrode are provided. Then, in applying plasma treatment to an article 7 to be processed, by regulating the intensity of the stationary magnetic field H, plasma conditions between the electrodes and in the vicinity of the surface of electrodes can be controlled and the concn., the distribution as well as the variety of main reactive sources related to the plasma reaction can be controlled.

60. 发明专利

JPS5624949A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5624949A
公开(公告)日：1981-03-10
申请号：JP10099279
申请日：1979-08-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： SAKURAI HIROMI , TSUBOUCHI NATSUO , AKIYAMA TOSHIHIKO
IPC分类号： H01L21/3205 , H01L21/28 , H01L29/43
摘要： PURPOSE:To eliminate the disconnection of wires formed on the semiconductor device by coating an insulating film having an opening on a semiconductor substrate, growing a semiconductor layer on the entire surface, forming a polycrystalline layer on the insulating film, doping impurity on unnecessary portion, and then etching it to remove it, thereby obtaining a flat surface thereon. CONSTITUTION:An n type buried region 3 and a p+ type channel breakdown region 4 surrounding the region 3 are formed in a p type Si substrate, and an SiO2 film 2 having an opening is coated on the region 3 thereon. Then, an n type layer is grown on the entire surface, monocrystalline layer 5a and polycrystalline layer 5b are formed respectively on the region 3 and the film 2, a p type impurity is diffused in the entire surface, and shallow and deep layers 51a and 51b are formed respectively in the layers 5a and 5b by utilizing the stepwise difference between the monocrystal and the polycrystal. Thereafter, it is heat treated to alter them into an oxide film 52 swelled in volume, and is etched and removed to obtain approximately flat layers 5a and 5b. Subsequently, the layer 5b is formed in desired shape, p type base region 7b or the like is formed thereon, and wire layer is formed on the entire surface thereof.

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