专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明专利

JPS60103559A VIDEO SIGNAL REPRODUCING DEVICE 失效
公开(公告)号：JPS60103559A
公开(公告)日：1985-06-07
申请号：JP21130683
申请日：1983-11-10
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO YOSHIYUKI , KAKIMOTO TAKASHI
IPC分类号： H04N5/94 , G11B20/06 , H04N5/93
摘要： PURPOSE:To suppress white noise on a reproduced pattern and also to prevent a normal signal from being spoiled by controlling the amplitude limit level of a video signal amplitude limit circuit in response to an output level of an envelope detection circuit to prevent buzz sound. CONSTITUTION:When missing of signal for a comparatively long period as shown in Fig. (a) takes place in a reproduced FM signal, each output of a missing signal compensating circuit 5, a limiter 6 and an FM demodulation circuit 7 is as shown in Figs. b-d respectively. On the other hand, the output of the envelope detection circuit 46 is as shown in Fig. (f), and an output of a white level amplitude limit circuit 47 is as shown in Fig. (g), where the amplitude limit level of the white level amplitude limit circuit 47 when the output of the envelope detection circuit is at high level and low level is VH and VL respectively. In reproducing the signal like this, since gray noise is obtained, the noise becomes unremarkable comparatively. In reproducing a picture through the connection of a television receiver to an RF output terminal 11, an RF converter 10 does not cause overmodulation.

52. 发明专利

JP2006173164A Sheet capacitor and manufacturing method thereof 审中-公开
标题翻译：其电容器及其制造方法
公开(公告)号：JP2006173164A
公开(公告)日：2006-06-29
申请号：JP2004359416
申请日：2004-12-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAMAMOTO YOSHIYUKI , MIKI KATSUMASA , SUGAYA YASUHIRO
IPC分类号： H01G9/028 , H01G9/00
摘要： PROBLEM TO BE SOLVED: To improve the manufacturing efficiency of sheet capacitor.
SOLUTION: The manufacturing method of the sheet capacitor comprises steps of forming a dielectric material film 2 on a sheet electrode 3, forming thereafter a small electrode 1 to a part of the dielectric material film 2, forming next a first solid-state electrolytic layer 5 through chemical oxidation polymerization on the small electrode 1 and the dielectric material film 2, forming moreover a second solid-state electrolytic layer 6 through electrolytic polymerization on the upper surface of the first solid-state electrolytic layer 5, and thereafter removing the small electrode 1 by forming a through-hole with the inclusion of the small electrode 1 up to the sheet electrode 3 from the second solid-state electrolytic layer 6.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高片式电容器的制造效率。解决方案：片状电容器的制造方法包括以下步骤：在片状电极3上形成电介质材料膜2，然后在电介质材料膜2的一部分上形成小电极1，形成第一固态电解质层5通过化学氧化聚合在小电极1和电介质材料膜2上，并通过电解聚合在第一固态电解质层5的上表面上形成第二固体电解质层6，然后除去小电极1通过从第二固体电解质层6形成包含小电极1直到片状电极3的通孔。（C）2006年，JPO＆NCIPI

53. 发明专利

JP2006165152A Solid electrolytic capacitor and substrate with built-in solid electrolytic capacitor, and those manufacturing methods 有权
标题翻译：固体电解电容器和具有内置固体电解电容器的基板及其制造方法
公开(公告)号：JP2006165152A
公开(公告)日：2006-06-22
申请号：JP2004352412
申请日：2004-12-06
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ASAHI TOSHIYUKI , SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI , MIKI KATSUMASA , KATSUMATA MASAAKI
IPC分类号： H01G9/012 , H01G9/00 , H01G9/14 , H01G9/26
摘要： PROBLEM TO BE SOLVED: To increase the capacity of low ESL capacitor by achieving structure where the capacitor positive pole and the capacitor negative pole are arranged in opposite positions while maintaining low ESL.
SOLUTION: A negative pole 105 and a positive pole 101 arranged to the opposed position are constituted such that the structure pulled out to the negative pole 105 side is achieved by a through-hole electrode 106 formed in the central part.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了通过实现电容器正极和电容器负极排列在相反位置同时保持低ESL的结构来增加低ESL电容器的容量。解决方案：布置在相对位置的负极105和正极101被构造成使得拉出到负极105侧的结构由形成在中心部分的通孔电极106实现。版权所有（C）2006，JPO＆NCIPI

54. 发明专利

JP2005039227A Module with built-in semiconductor, and its manufacturing method 审中-公开
标题翻译：具有内置半导体的模块及其制造方法
公开(公告)号：JP2005039227A
公开(公告)日：2005-02-10
申请号：JP2004177140
申请日：2004-06-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KOJIMA TOSHIYUKI , NAKATANI SEIICHI , SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI
IPC分类号： H01L23/28 , H01L23/12 , H01L23/52 , H01L25/04 , H01L25/18
CPC分类号： H01L23/3121 , H01L23/315 , H01L2224/16225 , H01L2224/73203 , H01L2224/83192 , H01L2924/09701 , H01L2924/19041 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To realize a high-density module by locating inner via-holes closer to a semiconductor device in a module with built-in semiconductor. SOLUTION: After the semiconductor device (105) is mounted on a surface of a first wiring layer (102a) formed on a circuit board (103), without performing a sealing process using sealing resin, an electric insulation base having an opening which has a through-hole (inner via-hole) (104) filled with a conductive paste in advance, and accommodates the semiconductor device, and a separation carrier on which a second wiring layer (102b) has been formed, are laminated, heated and pressurized. Thus, the module is obtained, in which the semiconductor device (105) is built in a core layer (101) consisting of an cured electric insulation base, and in which a space (107) is formed between the semiconductor device (105) and the first wiring layer (102a). COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过在内置半导体的模块中定位靠近半导体器件的内部通孔来实现高密度模块。解决方案：在半导体器件（105）安装在形成在电路板（103）上的第一布线层（102a）的表面上之后，不使用密封树脂进行密封处理，具有开口其具有预先填充有导电膏的通孔（内部通孔）（104），并且容纳半导体器件，并且在其上形成有第二布线层（102b）的分离载体层叠，加热并加压。因此，获得了其中半导体器件（105）被构建在由固化的电绝缘基底构成的芯层（101）中并且其中在半导体器件（105）和第一布线层（102a）。版权所有（C）2005，JPO＆NCIPI

55. 发明专利

JP2005011874A Module with built-in semiconductor and its manufacturing method 有权
标题翻译：具有内置半导体的模块及其制造方法
公开(公告)号：JP2005011874A
公开(公告)日：2005-01-13
申请号：JP2003171903
申请日：2003-06-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KOJIMA TOSHIYUKI , NAKATANI SEIICHI , SUGAYA YASUHIRO , YAMAMOTO YOSHIYUKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16 , H01L2224/29007 , H01L2224/73204 , H01L2224/83192 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701
摘要： PROBLEM TO BE SOLVED: To provide a module with a built-in semiconductor which is improved in density by arranging inner vias close to a semiconductor element. SOLUTION: The semiconductor element (4) is mounted on the surface of a wiring layer (2a) formed on a release carrier or a circuit board. The semiconductor element (4) and the wiring layer (2a) are sealed up with resin so as to position joints between the wiring layer (2a) and the semiconductor element (4) to overlap the outer edge of a sealing resin (6) partially with the outer edge of the semiconductor element (4), or to set inside the outer edge of the semiconductor element (4). Another release carrier, where an electric insulating base material which is provided with a through-hole (inner via) (3) previously filled up with conductive paste and with an opening for housing the semiconductor element, and a wiring layer (2b) are formed, is laminated thereon and pressed while heated. By this setup, the module where the semiconductor element (4) is built in a core layer (1) formed by curing the electric insulating base material is obtained. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供具有通过布置靠近半导体元件的内部通孔而提高密度的内置半导体的模块。解决方案：半导体元件（4）安装在形成在释放载体或电路板上的布线层（2a）的表面上。半导体元件（4）和布线层（2a）用树脂密封，以便在布线层（2a）和半导体元件（4）之间定位接合部分，以与部分地密封树脂（6）的外边缘重叠与半导体元件（4）的外边缘相连，或者设置在半导体元件（4）的外边缘内。形成有电绝缘基材的另一释放载体，其中设置有预先填充有导电浆料的通孔（内通孔）（3）和用于容纳半导体元件的开口的电绝缘基材和布线层（2b），并在加热的同时进行压制。通过这种设置，获得半导体元件（4）构建在通过固化电绝缘基材形成的芯层（1）中的模块。版权所有（C）2005，JPO＆NCIPI

56. 发明专利

JPH06335015A COLOR SIGNAL AUTOMATIC GAIN ADJUSTMENT CIRCUIT 失效
公开(公告)号：JPH06335015A
公开(公告)日：1994-12-02
申请号：JP12250893
申请日：1993-05-25
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IGAWA TAKAAKI , YAMAMOTO YOSHIYUKI
IPC分类号： H04N9/455 , H04N9/68
摘要： PURPOSE:To obtain an ACC circuit in which a burst level is kept to a predetermined value and the S/N is not deteriorated by solving a problem that a burst level of an RFC signal being an output of the ACC circuit is fluctuated and the S/N is deteriorated because post-stage digital color signal reproduction processing cannot absorb the fluctuation in the burst level when a recorded color signal level is changed. CONSTITUTION:The circuit is provided with a gain control circuit 2 varying a gain of an input signal, a burst amplifier circuit amplifying only the gain of a burst signal included in an output signal of a gain control circuit 2 in response to a control input terminal 14, and a level detection circuit 4 detecting an output level of the burst amplifier circuit. Then an output of the level detection circuit 4 controls the gain of the gain control circuit 2 to select the amplification factor of the burst amplifier circuit by a signal at a control input terminal 13.

57. 发明专利

JPH04341901A HEAD CURRENT ADJUSTING DEVICE AND MAGNETIC RECORDING/ REPRODUCING DEVICE 失效
公开(公告)号：JPH04341901A
公开(公告)日：1992-11-27
申请号：JP11297691
申请日：1991-05-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IKATA KOICHI , YAMAMOTO YOSHIYUKI
IPC分类号： G11B5/02 , G11B5/00 , G11B5/008 , G11B5/035 , G11B5/455
摘要： PURPOSE:To provide a head current adjusting device for keeping high sound quality and high picture quality in spite of the progress of the wear of a magnetic head and a VTR using the same in respect of a high sound quality VTR in which a sound signal is FM/deeplayer-recorded. CONSTITUTION:The progress of the wear of the head is known by detecting the change of a head current accompanying the wear of the head by using a bridge circuit including an inductor 12, a rotary transformer circuit 6 including the magnetic head 7, resistors 10, 13, and a differential amplifier 14. Then, the demagnetization of a preceding sound recording layer is suppressed by controlling the head current by a loop including a detector 15, a DC amplifier 16, a gain control amplifier 4, and a recording amplifier 5, and simultaneously, the head current is kept at an optimum value.

58. 发明专利

JPH04104596A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH04104596A
公开(公告)日：1992-04-07
申请号：JP22312290
申请日：1990-08-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO YOSHIYUKI
IPC分类号： H04N9/87
摘要： PURPOSE:To obtain a video signal processor where the time between a luminance signal and a chrominance signal is not changed even when switching the peaking frequency of a picture quality adjustment circuit utilizing a delay device by changing the delay time of the chrominance signal to be inputted to a chrominance signal processing circuit corresponding to it even when different peaking frequencies are selected. CONSTITUTION:The amount of stress of a frequency characteristic changeover circuit 11 is controlled by a first control signal supplied to a first control terminal 5, and the circuit 11 is equipped with first and second picture quality adjustment circuits 12 and 13 with peaking frequencies different each other and a switch circuit 14 selecting the output. In this case, the delay time of a delay device 17 is the same as the one of the picture quality adjustment circuit 12, and the delay time of a delay device 18 is the same as the one of the picture quality adjustment circuit 13. The output of a switch circuit 19 is supplied to a chrominance signal processing circuit 7 and outputted from a chrominance signal output terminal 8 after prescribed processing. Thus, the time difference between the luminance signal whose picture quality is adjusted and the chrominance signal adjusted by the chrominance signal processing circuit can be eliminated.

59. 发明专利

JPH0340669A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPH0340669A
公开(公告)日：1991-02-21
申请号：JP17589389
申请日：1989-07-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IGAWA TAKAAKI , YAMAMOTO YOSHIYUKI
IPC分类号： H04N5/208
摘要： PURPOSE:To prevent synchronization of a television receiver from being disturbed by eliminating horizontal and vertical synchronizing signal of an inputted Y signal so as to apply contour emphasis in the vertical direction thereby inhibiting the contour emphasis for the period of the synchronizing signal. CONSTITUTION:When a Y signal is inputted at first to an input terminal 1, Y signals retarded by 1H and 2H respectively to inputs are outputted from an output of a 1st 1H delay element 2 and an output of a 2nd 1H delay element 4. When the input Y signal (a), retarded Y signals b, c delayed by 1H, 2H respectively are inputted respectively to clamp circuits 10, 12, 14 and SYNC clip circuits 11, 13, 15, a horizontal synchronizing signal and a vertical synchronizing signal are eliminated from the output. A luminance difference signal (g) outputted from a subtractor 6 is added to a Y signal (b) retarded by 1H at a prescribed level and then a Y signal whose vertical contour is emphasized is outputted from an adder 5.

60. 发明专利

JPH01268294A VIDEO SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH01268294A
公开(公告)日：1989-10-25
申请号：JP9603488
申请日：1988-04-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMAMOTO YOSHIYUKI
IPC分类号： H04N9/83
摘要： PURPOSE:To erase interference from a luminance signal to a color burst signal when separated luminance signal and chrominance signal are mixed again and to prevent the band degradation of the luminance signal during a period to be displayed on a screen by band-limiting the frequency band of the separated luminance signal only during a color burst signal period. CONSTITUTION:The output of a mono-multiplier circuit 11 is set to be wider than the color burst signal period by the degree of 0.5 to 1.0musec before and after the period and the output of a low-pass filter 8 is operated so as to be conducted to the output of a signal switch 7 only during the period. Accordingly, the frequency band of the luminance signal is band-limited only during the color burst signal period and the interference from the luminance signal to the color burst signal is widely suppressed. Thus, with simple constitution, the band degradation of the luminance signal is completely erased during the period to be displayed on the screen and further, the interference from the luminance signal to the color burst signal can be almost erased.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式