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51. 发明申请

US20100032759A1 SELF-ALIGNED SOI SCHOTTKY BODY TIE EMPLOYING SIDEWALL SILICIDATION 审中-公开
标题翻译：自对准SOI肖特基身体采用侧壁硅酸盐
公开(公告)号：US20100032759A1
公开(公告)日：2010-02-11
申请号：US12189639
申请日：2008-08-11
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel.
摘要翻译：自对准硅绝缘体（SOI）肖特基体系结构包括：源极区，包括设置在源极区的顶表面上的硅化物层; 漏极区，包括设置在所述漏极区的顶表面上的硅化物层; 栅极区域，设置在由漏极和源极区域形成的沟道上方; 以及栅极氧化物层，其设置在由漏极和源极区域形成的栅极区域和沟道之间，其中当对扩散区域进行硅化时，其形成金属 - 硅合金接触，使得硅化物层延伸到沟道中并直接接触沟道。

52. 发明申请

US20100006956A1 Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same 有权
标题翻译：具有硅侧壁的金属高K晶体管用于减少寄生电容，以及制造相同的工艺
公开(公告)号：US20100006956A1
公开(公告)日：2010-01-14
申请号：US12539842
申请日：2009-08-12
申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/517 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
摘要翻译：公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。耗尽的侧壁层是非晶硅或多晶硅之一。该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

53. 发明申请

US20090224335A1 FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT 失效
标题翻译：具有减少的低温分离分离诱发的漏电流的场效应晶体管
公开(公告)号：US20090224335A1
公开(公告)日：2009-09-10
申请号：US12041967
申请日：2008-03-04
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译：沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

54. 发明申请

US20080303105A1 DUAL GATE DIELECTRIC SRAM 失效
标题翻译：双门电介质SRAM
公开(公告)号：US20080303105A1
公开(公告)日：2008-12-11
申请号：US11759538
申请日：2007-06-07
申请人： Leland Chang , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/76 , H01L21/44
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance.
摘要翻译：提供了包含具有比NFET栅极电介质更厚的有效氧化物厚度（EOT）的PFET栅极电介质的SRAM单元结构及其制造方法。 PFET栅极电介质和NFET栅极电介质可以是氮氧化硅层，CVD氧化物层或具有不同厚度的高K电介质层。 PFET栅极电介质可以是两个电介质层的堆叠，并且NFET栅极电介质可以是两个电介质层中的一个。 PFET栅极电介质的更大的EOT产生上拉PFET的导通电流的降低，以获得最佳的SRAM性能。

55. 发明申请

US20070249133A1 CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING 审中-公开
标题翻译：用于半导体器件的导电间隔物
公开(公告)号：US20070249133A1
公开(公告)日：2007-10-25
申请号：US11308604
申请日：2006-04-11
申请人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
发明人： Gary Bronner , David Fried , Jeffrey Gambino , Leland Chang , Ramachandra Divakaruni , Haizhou Yin , Gregory Costrini , Viraj Sardesai
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/28518 , H01L21/76895 , H01L21/823468 , H01L21/84 , H01L27/11 , H01L27/1108 , H01L27/1203
摘要： A method of forming a conductive spacer on a semiconductor device. The method includes depositing a polysilicon layer on the semiconductor device, selectively implanting dopant ions in the polysilicon layer on a first side of a transistor region of the semiconductor device to define a conductive spacer area, and removing the polysilicon layer except for the conductive spacer area. Optionally, a silicidation process can be performed on the conductive spacer area so that the conductive spacer is made up of metal silicide.
摘要翻译：一种在半导体器件上形成导电间隔物的方法。该方法包括在半导体器件上沉积多晶硅层，在半导体器件的晶体管区域的第一侧上选择性地将多晶硅层中的掺杂剂离子注入以限定导电间隔区，以及除去导电间隔区之外的多晶硅层。任选地，可以在导电间隔物区域上进行硅化处理，使得导电间隔物由金属硅化物构成。

56. 发明申请

US20070242513A1 Static random access memory (SRAM) cells 有权
标题翻译：静态随机存取存储器（SRAM）单元
公开(公告)号：US20070242513A1
公开(公告)日：2007-10-18
申请号：US11402401
申请日：2006-04-12
申请人： Leland Chang , Rajiv Joshi , Stephen Kosonocky
发明人： Leland Chang , Rajiv Joshi , Stephen Kosonocky
IPC分类号： G11C16/04
CPC分类号： G11C11/412
摘要： The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.
摘要翻译：本发明提供一种改进的SRAM单元。具体地说，本发明提供一种具有一组或多组堆叠晶体管的SRAM单元，用于在读取操作期间隔离单元。根据实施例，本发明的SRAM单元可以具有八个或十个晶体管。无论如何，本发明的SRAM单元通常包括分离/去耦合的写字和读字线，一对交叉耦合的反相器和耦合到写字线的互补的一对通过晶体管。在SRAM单元中实现的每组堆叠晶体管具有耦合到位线以及读取字线的晶体管。

57. 发明授权

US07242629B2 High speed latch circuits using gated diodes 有权
标题翻译：使用门控二极管的高速锁存电路
公开(公告)号：US07242629B2
公开(公告)日：2007-07-10
申请号：US11491701
申请日：2006-07-24
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
IPC分类号： G11C7/00 , G11C7/02 , G01R19/00 , H03F3/60
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译：读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

58. 发明授权

US07136296B2 Static random access memory utilizing gated diode technology 有权
公开(公告)号：US07136296B2
公开(公告)日：2006-11-14
申请号：US11067797
申请日：2005-02-28
申请人： Wing Kin Luk , Leland Chang
发明人： Wing Kin Luk , Leland Chang
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have high signal to noise ratio, high signal margin, and tolerance to process variations, to form a single high performance static memory cell. This new cell has independent read and write paths, which allow for separate optimization of the read (R) and write (W) events, and enable dual-port R/W operation. Furthermore, storage node disturbance during the read and write operations are eliminated, which greatly improves cell stability and scalability for future technologies.

59. 发明授权

US07106620B2 Memory cell having improved read stability 有权
标题翻译：具有改善的读稳定性的存储单元
公开(公告)号：US07106620B2
公开(公告)日：2006-09-12
申请号：US11069018
申请日：2005-02-28
申请人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
发明人： Leland Chang , Robert H. Dennard , Robert Kevin Montoye
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译：用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。

60. 发明授权

US08835997B2 Low extension dose implants in SRAM fabrication 有权
标题翻译： SRAM制造中的低延伸剂量植入物
公开(公告)号：US08835997B2
公开(公告)日：2014-09-16
申请号：US13464267
申请日：2012-05-04
申请人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
发明人： Leland Chang , Chung-Hsun Lin , Shih-Hsien Lo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L27/0207 , H01L27/1104 , H01L29/6659
摘要： A static random access memory fabrication array includes at least one p-type field effect transistor, including a gate stack and isolating spacers forming a gate having a gate length Lgate and an effective gate length, Leff and a source and drain region adjacent the gate stack, wherein the source and drain regions are formed from a low extension dose implant that decreases a difference between Lgate and Leff.
摘要翻译：静态随机存取存储器制造阵列包括至少一个p型场效应晶体管，其包括栅极堆叠和形成具有栅极长度L gate和有效栅极长度的栅极的隔离间隔，Leff以及与栅极堆叠相邻的源极和漏极区域其中源极和漏极区域由低延伸剂量植入物形成，其降低了Lgate和Leff之间的差异。

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