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51. 发明授权

US06618288B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06618288B2
公开(公告)日：2003-09-09
申请号：US10265106
申请日：2002-10-07
申请人： Takao Akaogi , Yasushi Kasa
发明人： Takao Akaogi , Yasushi Kasa
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

52. 发明授权

US06566938B2 System for a constant current source 有权
公开(公告)号：US06566938B2
公开(公告)日：2003-05-20
申请号：US09916972
申请日：2001-07-27
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G05F110
CPC分类号： G05F1/618
摘要： A system for a constant current source circuit utilizing CMOS technology. The system includes a constant current source circuit that includes a bias circuit that outputs a bias signal and a switch circuit that has a switch input coupled to receive the bias signal, a switch output, and a switch control that is coupled to receive an input signal. The current source circuit also includes an output circuit that has a first input coupled to the switch output and a second input coupled to the input signal. The output circuit provides an output signal that has constant current.

53. 发明授权

US06563738B2 Nonvolatile semiconductor memory device having electrically and collectively erasable characteristics 失效
公开(公告)号：US06563738B2
公开(公告)日：2003-05-13
申请号：US10150017
申请日：2002-05-20
申请人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
发明人： Takao Akaogi , Nobuaki Takashina , Yasushi Kasa , Kiyoshi Itano , Hiromi Kawashima , Minoru Yamashita
IPC分类号： G11C1604
CPC分类号： G11C29/80 , G11C5/145 , G11C7/067 , G11C8/00 , G11C8/08 , G11C8/10 , G11C16/04 , G11C16/0416 , G11C16/08 , G11C16/10 , G11C16/107 , G11C16/12 , G11C16/16 , G11C16/26 , G11C16/30 , G11C16/3404 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C16/3472 , G11C16/3481 , G11C29/028 , G11C29/34 , G11C29/46 , G11C29/50 , G11C29/50004 , G11C29/802 , G11C29/82 , G11C29/88 , G11C2029/5004
摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

54. 发明授权

US06542415B2 Kickb signal generator 有权
标题翻译：踢脚号信号发生器
公开(公告)号：US06542415B2
公开(公告)日：2003-04-01
申请号：US09932077
申请日：2001-08-17
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C700
CPC分类号： G11C8/18
摘要： A signal generator for generating a kickb signal used to reset a boost signal used to operate a memory device. The signal generator includes an address detector that receives one or more address lines and a clock signal to produce a detector output. A switch circuit is also included that receives the detector output, the clock signal and a feedback signal to produce a switch output. A delay circuit is coupled to receive the switch output to produce a delayed switch output, and an output circuit is coupled to receive the switch output and the delayed switch output to produce the kickb signal, where the kickb signal forms the feedback signal.
摘要翻译：一种用于产生用于复位用于操作存储器件的升压信号的脚踏信号的信号发生器。信号发生器包括地址检测器，其接收一个或多个地址线和时钟信号以产生检测器输出。还包括接收检测器输出，时钟信号和反馈信号以产生开关输出的开关电路。延迟电路被耦合以接收开关输出以产生延迟的开关输出，并且输出电路被耦合以接收开关输出和延迟的开关输出以产生脚踏信号，其中脚踏信号形成反馈信号。

55. 发明授权

US06246609B1 Decoder circuit 有权
标题翻译：解码电路
公开(公告)号：US06246609B1
公开(公告)日：2001-06-12
申请号：US09365071
申请日：1999-07-30
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C1134
CPC分类号： G11C8/18 , G11C16/08 , G11C16/30 , G11C16/32
摘要： A decoder circuit has two separate portions, a low voltage portion and a high voltage portion. Through the use of the high voltage portion, the decoder circuit is capable of supplying high program voltage. Through the use of low voltage portion and isolated from the high voltage portion, quick read operation is performed.
摘要翻译：解码器电路具有两个分开的部分，即低电压部分和高电压部分。通过使用高压部分，解码器电路能够提供高编程电压。通过使用低电压部分并与高压部分隔离，进行快速读取操作。

56. 发明授权

US06185128B2 Reference cell four-way switch for a simultaneous operation flash memory device 有权
标题翻译：参考单元四路开关，用于同时运行闪存设备
公开(公告)号：US06185128B2
公开(公告)日：2001-02-06
申请号：US09421984
申请日：1999-10-19
申请人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
发明人： Tien-Min Chen , Kazuhiro Kurihara , Takao Akaogi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C16/3436 , G11C2216/22
摘要： A flash memory system capable of simultaneous operation comprises upper and lower memory banks of flash memory cells, reference cells generating reference signals, a switch coupled to the reference cells and upper and lower sense amplifiers coupled to the switch and to the upper and lower memory bank, respectively. The switch steers the appropriate reference signal to the appropriate upper sense amplifier along one upper signal line and steers the appropriate reference signal to the appropriate lower sense amplifier along a lower signal line. The upper and lower sense amplifiers generate comparison signals in response to reference signals and data stored in the upper and lower memory bank, respectively.
摘要翻译：能够同时操作的闪速存储器系统包括闪存单元的上部和下部存储器组，产生参考信号的参考单元，耦合到参考单元的开关和耦合到该开关的上部和下部读出放大器以及上部和下部存储器组，分别。开关将适当的参考信号沿着一个上部信号线转向适当的上部读出放大器，并将适当的参考信号沿着较低的信号线转向适当的下部读出放大器。上和下感测放大器响应于分别存储在上部和下部存储体中的参考信号和数据产生比较信号。

57. 发明授权

US6118698A Output multiplexing implementation for a simultaneous operation flash memory device 有权
标题翻译：用于同时运行的闪存设备的输出多路复用实现
公开(公告)号：US6118698A
公开(公告)日：2000-09-12
申请号：US422199
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C16/26 , G11C16/28 , G11C16/04
CPC分类号： G11C16/26 , G11C16/28
摘要： A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.
摘要翻译：公开了一种包括用于复用的读出放大器输出信号路径的同步电路的闪存芯片。同步电路包括信号发生器，读出放大器和输出多路复用器。来自读出放大器的数据到达输出多路复用器是相等的。通过调整信号路径长度，从而从信号发生器到读出放大器的信号路径长度的电阻和电容来实现均衡，该读出放大器承载信号以使读出放大器将其数据传输到输出多路复用器。

58. 发明授权

US5910916A Flash-erasable semiconductor memory device having improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US5910916A
公开(公告)日：1999-06-08
申请号：US986339
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

59. 发明授权

US5835416A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5835416A
公开(公告)日：1998-11-10
申请号：US986338
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

60. 发明授权

US5608670A Flash memory with improved erasability and its circuitry 失效
标题翻译：闪存具有改进的可擦除性及其电路
公开(公告)号：US5608670A
公开(公告)日：1997-03-04
申请号：US436721
申请日：1995-05-08
申请人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
发明人： Takao Akaogi , Hiromi Kawashima , Tetsuji Takeguchi , Ryoji Hagiwara , Yasushi Kasa , Kiyoshi Itano , Yasushige Ogawa , Shouichi Kawamura
IPC分类号： G05F3/20 , G11C5/14 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/16 , G11C16/30 , G11C29/00 , H03K3/356 , H03K19/0185 , H03K19/21
CPC分类号： G11C29/82 , G05F3/205 , G11C16/0416 , G11C16/08 , G11C16/16 , G11C16/30 , G11C5/145 , H03K19/018521 , H03K19/215 , H03K3/356147 , H03K3/356165
摘要： The present invention relates to improvements in erasing a flash memory. An object of the present invention is to shorten the erasing time. During pre-erase writing, at least either word lines or bit lines are selected in units of multiple lines at a time, and data are written in multiple selective transistors simultaneously.
摘要翻译：本发明涉及擦除闪存的改进。本发明的目的是缩短擦除时间。在预擦除写入期间，一次以多行单位选择字线或位线中的至少一个，并且数据被同时写入多个选择晶体管。

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