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51. 发明授权

US06781839B2 Vertical surface mount apparatus with thermal carrier and method 失效
标题翻译：具有热载体和方法的垂直表面贴装装置
公开(公告)号：US06781839B2
公开(公告)日：2004-08-24
申请号：US10457122
申请日：2003-06-09
申请人： Larry D. Kinsman , Jerry M. Brooks , Walter L. Moden
发明人： Larry D. Kinsman , Jerry M. Brooks , Walter L. Moden
IPC分类号： H05K720
CPC分类号： H05K3/303 , H01L23/3675 , H01L23/4334 , H01L2924/0002 , H05K1/0203 , H05K2201/09709 , H05K2201/10454 , H05K2201/10659 , H05K2201/10696 , Y02P70/613 , H01L2924/00
摘要： A high density vertical surface mount package and thermal carrier therefore including a heat sink.
摘要翻译：因此，高密度垂直表面安装封装和热载体包括散热器。

52. 发明授权

US06765803B2 Semiconductor device socket 失效
标题翻译：半导体器件插座
公开(公告)号：US06765803B2
公开(公告)日：2004-07-20
申请号：US10202539
申请日：2002-07-23
申请人： Warren M. Farnworth , Larry D. Kinsman , Walter L. Moden
发明人： Warren M. Farnworth , Larry D. Kinsman , Walter L. Moden
IPC分类号： H05K714
CPC分类号： H05K7/1007 , H01R12/89
摘要： A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.
摘要翻译：基本上相对于载体基板垂直地固定裸露和最小封装的半导体器件的插座。插座包括中间导电元件和在插入位置和偏置位置之间移动中间导电元件的构件。在将中间导电元件放置到插入位置之后，可以以最小的插入力将半导体器件插入到插座的插座中。将构件移动到偏置位置有助于中间导电元件抵靠半导体器件的接合焊盘的偏置。中间导电元件在半导体器件和载体衬底之间建立电连接。插座的第一实施例包括相对于插座的其余部分横向移动的构件。在插座的第二实施例中，构件相对于插座体垂直移动。

53. 发明授权

US06737734B2 Structure and method for securing bussing leads 失效
标题翻译：用于固定总线的结构和方法
公开(公告)号：US06737734B2
公开(公告)日：2004-05-18
申请号：US10407648
申请日：2003-04-04
申请人： Jerry M. Brooks , Larry D. Kinsman , Timothy J. Allen
发明人： Jerry M. Brooks , Larry D. Kinsman , Timothy J. Allen
IPC分类号： H01L23495
CPC分类号： H01L23/4951 , H01L2924/0002 , H01L2924/00
摘要： A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extend over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.
摘要翻译：具有用于常规引线到I / O引线接合的引线和在半导体管芯的表面上延伸的用于电源和接地总线的引线的混合引线框架设置在用于总线的引线通过引线锁带以防止制造过程中的总线引线的弯曲和/或其他移动。更具体地，引线锁带横向地安装在靠近模具附接位置和外部的多个总线引线上。

54. 发明授权

US06700206B2 Stacked semiconductor package and method producing same 有权
标题翻译：叠层半导体封装及其制造方法
公开(公告)号：US06700206B2
公开(公告)日：2004-03-02
申请号：US10211021
申请日：2002-08-02
申请人： Larry D. Kinsman
发明人： Larry D. Kinsman
IPC分类号： H01L23495
CPC分类号： H01L23/49575 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01079 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. The active surface of a first semiconductor die is adhered to the underside of the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die may be adhered to the upper side of the die paddle along a surface which is opposite to its active surface and is electrically coupled with one or more of the plurality of lead fingers. The die paddle may be formed to exhibit a smaller peripheral outline than that of the first semiconductor die such that the die paddle does not interfere with any peripherally located bond pads of the first semiconductor die. The die paddle may further serve as a heat spreader, resulting in a more thermally stable package.
摘要翻译：一种半导体器件封装及其制造方法。该封装包括具有管芯焊盘和多个引线指的引线框架。第一半导体管芯的有源表面粘附到管芯焊盘的下侧，并且与多个引线指中的一个或多个电连接。第二半导体管芯可以沿着与其有源表面相对的表面粘附到管芯焊盘的上侧，并且与多个引线指中的一个或多个电连接。模板可以被形成为具有比第一半导体管芯更小的周边轮廓，使得管芯焊盘不干扰第一半导体管芯的任何外围定位的焊盘。模片可以进一步用作散热器，从而产生更加热稳定的包装。

55. 发明授权

US06600215B1 Method and apparatus for coupling a semiconductor die to die terminals 失效
公开(公告)号：US06600215B1
公开(公告)日：2003-07-29
申请号：US09054275
申请日：1998-04-02
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

56. 发明授权

US06558966B2 Apparatus and methods of packaging and testing die 有权
公开(公告)号：US06558966B2
公开(公告)日：2003-05-06
申请号：US09851657
申请日：2001-05-08
申请人： Leonard E. Mess , David J. Corisis , Walter L. Moden , Larry D. Kinsman
发明人： Leonard E. Mess , David J. Corisis , Walter L. Moden , Larry D. Kinsman
IPC分类号： H01L2166
CPC分类号： H01L22/26 , H01L23/055 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L2224/05554 , H01L2224/05599 , H01L2224/16225 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49171 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06517 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06596 , H01L2924/00014 , H01L2924/01322 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2224/45099
摘要： Apparatus and methods of packaging and testing die. In one embodiment, a stacked die package includes a packaging substrate having a first surface with a recess disposed therein and a plurality of conductive leads coupled thereto, a first die attached to the packaging substrate within the recess and having a plurality of first bond pads electrically coupled to at least some of the conductive leads, and a second die attached to the first die and having a plurality of second bond pads that are electrically coupled to at least some of the conductive leads. When the stacked die package is engaged with, for example, a circuit board, the first surface of the packaging substrate is proximate the circuit board so that the packaging substrate at least partially encloses and protects the first and second die. The properties and dimensions of the packaging substrate are tailored to optimize the operational environment of the die, including improving thermal dissipation and enhancing performance of the die. In an alternate embodiment, the packaging substrate comprises an electrically conductive substrate and an electrically insulative material is formed between the conductive leads and the packaging substrate. In another embodiment, the first bond pads are electrically coupled to the conductive leads by wire-bonding. Alternately, the first bond pads are in direct contact with the conductive leads in a flip chip arrangement. In another embodiment, the die is sealed within an encapsulating layer to protect the first and second die.

57. 发明授权

US06555399B1 Double-packaged multichip semiconductor module 失效
标题翻译：双封装多芯片半导体模块
公开(公告)号：US06555399B1
公开(公告)日：2003-04-29
申请号：US08650894
申请日：1996-05-17
申请人： Alan G. Wood , Eugene H. Cloud , Larry D. Kinsman
发明人： Alan G. Wood , Eugene H. Cloud , Larry D. Kinsman
IPC分类号： G01R3126
CPC分类号： H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A method for forming a semiconductor component comprises packaging a plurality of semiconductor die into one component. Present designs comprise multiple unpackaged die which have been probed, but not rigorously tested for complete functionality and adherence to required operating specifications. The yields of present designs of multi-chip modules (MCMs) are low and functional units are therefore costly. Unlike present designs incorporating multiple die, the inventive design comprises devices which have been singularized, packaged, and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices are then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are enjoined with traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The I/O leads provide means for connecting the housing with the electronic device into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.
摘要翻译：一种用于形成半导体部件的方法包括将多个半导体管芯封装成一个部件。目前的设计包括已被探测的多个未封装的裸片，但没有经过严格测试以完成功能并遵守所需的操作规范。多芯片模块（MCM）的现有设计的成品率低，因此功能单元成本高昂。不同于结合多个管芯的现有设计，本发明的设计包括已被单一化，封装和彻底测试的功能性和遵守所需规格的器件。然后，多个封装的装置被壳体接收。封装器件的导电引线与制造在外壳中的焊盘电耦合。这些垫子在壳体内被带有痕迹，该痕迹从壳体外部终止。然后，输入/输出引线与迹线电耦合，或者当制造外壳时与引线耦合。 I / O引线提供用于将壳体与其所安装的电子设备连接的装置。由壳体容纳的盖子将封装的模具密封在壳体中，并且防止可能妨碍模具的正常功能的水分或其它污染物进入壳体。

58. 发明授权

US06541856B2 Thermally enhanced high density semiconductor package 有权
公开(公告)号：US06541856B2
公开(公告)日：2003-04-01
申请号：US09874011
申请日：2001-06-06
申请人： David J. Corisis , Mike Brooks , Mark S. Johnson , Larry D. Kinsman
发明人： David J. Corisis , Mike Brooks , Mark S. Johnson , Larry D. Kinsman
IPC分类号： H01L2972
CPC分类号： H01L25/0652 , H01L2224/4826
摘要： A high density semiconductor package with thermally enhanced properties is described. The semiconductor package includes a pair of lead frames, each being attached to a respective semiconductor die. The dies are attached to respective lead frames via an adhering material, such as a tape. Further, the dies are each electrically connected to fingers of each lead frame. In one illustrated embodiment, the dies and portions of the fingers are encapsulated in such a way as to leave one surface of each die exposed. In another illustrated embodiment, heat dissipation for the semiconductor package occurs through exposed fingers of the lead frames which adhere semiconductor dies within a cavity located therebetween.

59. 发明授权

US06528408B2 Method for bumped die and wire bonded board-on-chip package 有权
标题翻译：凸模和导线键合片上封装方法
公开(公告)号：US06528408B2
公开(公告)日：2003-03-04
申请号：US09863245
申请日：2001-05-21
申请人： Larry D. Kinsman
发明人： Larry D. Kinsman
IPC分类号： H01L2912
CPC分类号： H01L24/73 , H01L21/563 , H01L23/13 , H01L23/3114 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/85 , H01L24/91 , H01L2224/0401 , H01L2224/05599 , H01L2224/06135 , H01L2224/06136 , H01L2224/1134 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/1319 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/85 , H01L2224/85399 , H01L2224/92 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/3512 , H01L2224/45015 , H01L2924/207
摘要： A method and apparatus for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached face down to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires are attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby, allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.
摘要翻译：一种用于制造半导体组件的方法和装置，具体地，将半导体管芯互连到载体衬底。载体衬底包括第一表面和具有穿过其中的至少一个开口的第二表面。模具包括活性表面和后表面，其中模具面向下地附着到载体基底的第一表面上，其间具有导电凸块。此外，多个接合线通过载体衬底中的至少一个开口附着在管芯的有效表面和载体衬底的第二表面之间。通过这种布置，导电凸块和接合线都共同地在管芯和载体衬底之间的电互连中，从而允许用于接合焊盘的更多空间与接合线互连和/或允许更小的管芯尺寸。

60. 发明授权

US06507109B2 Vertical surface mount package utilizing a back-to-back semiconductor device module 失效
公开(公告)号：US06507109B2
公开(公告)日：2003-01-14
申请号：US10073487
申请日：2002-02-11
申请人： Larry D. Kinsman
发明人： Larry D. Kinsman
IPC分类号： H01L2334
CPC分类号： H01L25/0657 , H01L2225/06517 , H01L2225/0652 , H01L2225/06551 , H01L2225/06555 , H01L2225/06575 , H01L2225/06582 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , Y10T29/49126 , H01L2924/00
摘要： A back-to-back semiconductor device module including two semiconductor devices, the backs of each being secured to one another. The bond pads of both semiconductor devices are disposed adjacent a single, mutual edge of the device module. The device module may be secured to a carrier substrate in a substantially perpendicular orientation relative to the former. Solder reflow or a module-securing device can secure the device module to the carrier substrate. An embodiment of a module-securing device comprises an alignment device having one or more receptacles formed therein and intermediate conductive elements that are disposed within the receptacles to establish an electrical connection between the semiconductor devices and the carrier substrate. Another module-securing device comprises a clip-on lead, where one end resiliently biases against a lead of at least one of the semiconductor devices, while the other end connects electrically to a carrier substrate terminal.

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