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51. 发明申请

US20100133586A1 HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：异相双极晶体管及其形成方法
公开(公告)号：US20100133586A1
公开(公告)日：2010-06-03
申请号：US12463011
申请日：2009-05-08
申请人： Byoung-Gue MIN , Jong-Min Lee , Seong-II Kim , Kyung-Ho Lee , Hyung-Sup Yoon , Eun-Soo Nam
发明人： Byoung-Gue MIN , Jong-Min Lee , Seong-II Kim , Kyung-Ho Lee , Hyung-Sup Yoon , Eun-Soo Nam
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/42304 , H01L29/41708 , H01L29/66318 , H01L29/7371
摘要： Provided are a heterojunction bipolar transistor and a method of forming the same. The method includes forming an emitter electrode on an emitter capping pattern, a base electrode on a base pattern, and a collector electrode on a subcollector pattern, the subcollector pattern, the base pattern, an emitter pattern, and the emitter capping pattern being provided to a substrate; patterning a protection insulation layer and a first dummy pattern covering the emitter electrode, the base electrode, and the collector electrode, to expose the emitter electrode, the base electrode, and the collector electrode; forming a second dummy pattern to electrically separate the emitter electrode, the base electrode, and the collector electrode; forming, on the substrate provided with the second dummy pattern, an emitter electrode interconnection connected to the emitter electrode, a base electrode interconnection connected to the base electrode, and a collector electrode interconnection connected to the collector electrode; and removing the first and second dummy patterns.
摘要翻译：提供了一种异质结双极晶体管及其形成方法。该方法包括在发射极盖图案上形成发射电极，在基底图案上形成基极，在子集电极图案上形成集电极，将子集电极图案，基底图案，发射极图案和发射极封盖图案设置在底物; 图案化保护绝缘层和覆盖发射电极，基极和集电极的第一虚拟图案，以暴露发射极，基极和集电极; 形成第二虚设图形以电分离发射电极，基极和集电极; 在设置有第二虚设图案的基板上形成连接到发射极的发射极电极互连，与基极连接的基极互连和与集电极连接的集电极互连; 以及去除第一和第二虚拟图案。

52. 发明申请

US20070048711A1 Rf signal of karaoke data receiving pack and karaoke system using thereof 失效
标题翻译：使用卡拉OK数据接收包和卡拉OK系统的Rf信号
公开(公告)号：US20070048711A1
公开(公告)日：2007-03-01
申请号：US10560143
申请日：2004-06-10
申请人： Kyung-Ho Lee
发明人： Kyung-Ho Lee
IPC分类号： G09B5/00
CPC分类号： G09B19/00 , G10H1/0083 , G10H1/363 , G10H2240/211 , G11B27/105 , G11B31/00 , G11B2220/2562 , H04N5/84 , H04N21/42203 , H04N21/42646 , H04N21/4325 , H04N21/482
摘要： Disclosed are an RF signal of karaoke data receiving pack and karaoke system using thereof. The RF Karaoke data receiving pack includes an RF receiver for receiving a voice signal and key data signal radio-transmitted from a wireless microphone device via a receiving antenna; an audio/key data signal separator for separating the voice signal and key data signal from the signal demodulated by the demodulator; a receiver MCU controlling the internal operation of the RF karaoke data signal receiving pack while transmitting the digital voice signal and key data signal to the external computing device; and an extension pack in which additional songs are recorded, the extension pack being connected to an extension pack slot to transmit data of the additional songs under the control of the receiver MCU.
摘要翻译：公开了使用其的卡拉OK数据接收包和卡拉OK系统的RF信号。 RF卡拉OK数据接收包包括用于接收语音信号的RF接收器和经由接收天线从无线麦克风装置无线发送的密钥数据信号; 用于从由解调器解调的信号中分离语音信号和键数据信号的音频/键数据信号分离器; 接收机MCU，其在将数字语音信号和密钥数据信号发送到外部计算设备的同时控制RF卡拉OK数据信号接收包的内部操作; 以及其中记录附加歌曲的扩展包，扩展包连接到扩展包插槽，以在接收器MCU的控制下传送附加歌曲的数据。

53. 发明申请

US20060141714A1 Method for manufacturing a semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20060141714A1
公开(公告)日：2006-06-29
申请号：US11319814
申请日：2005-12-27
申请人： Kyung-Ho Lee
发明人： Kyung-Ho Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823814 , H01L21/823857 , H01L21/823892
摘要： An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.
摘要翻译：根据本发明的实施例的制造半导体器件的示例性方法包括在低电压/中压（LV / MV）下形成用于高压（HV）器件和第一阱的P阱和N阱，在半导体衬底中的逻辑器件的区域; 同时在用于逻辑器件的LV / MV区域中形成第二阱以及使用相同掩模的一个HV器件的漂移区域; 并分别在HV / MV / LV区域的半导体衬底上形成栅氧化层。根据本发明，通过用用于形成逻辑器件的典型阱的掩模替换或组合用于形成高电压耗尽增强CMOS（DECMOS）的扩展漏极区域的附加掩模，可以减少光刻工艺的数量，因此可以提高设备的整个过程的生产率。

54. 发明授权

US5496779A Method for fabricating a self-aligned T-gate metal semiconductor field effect transistor 失效
标题翻译：制造自对准T型栅极金属半导体场效应晶体管的方法
公开(公告)号：US5496779A
公开(公告)日：1996-03-05
申请号：US358886
申请日：1994-12-19
申请人： Kyung-Ho Lee , Youn-Kyu Bae , Kwang-Eui Pyun , Kyung-Soo Kim
发明人： Kyung-Ho Lee , Youn-Kyu Bae , Kwang-Eui Pyun , Kyung-Soo Kim
IPC分类号： H01L29/812 , H01L21/285 , H01L21/335 , H01L21/338 , H01L21/265
CPC分类号： H01L29/66878 , H01L21/28587
摘要： Disclosed is a method of fabricating a metal semiconductor field effect transistor, comprising the steps for, forming the channel using an ion-implantation, sequentially forming a first insulator layer at a first predetermined temperature and a second insulation layer at second predetermined temperature over the surface of the substrate, etching the first and second insulation layers using a gate pattern of a photo-resist pattern to expose the channel region as a mask, forming a refractory metal over the surface of the first and second insulation layer add the exposed channel region, etching the refractory metal, thereby dividing it into two parts of which one is formed on the channel region and the other is formed on the second insulation layer, selectively etching the first and second insulation layers to lift-off the refractory metal over the first and second insulation layers, thereby forming a gate of a T-shape on the channel region, ion implanting Si into a substrate using the gate and a channel pattern of a photo-resist film to form a self-aligned high concentration ion implantation region, forming a third insulation layer for preventing As of evaporation, carrying out a rapid thermal annealing for activation, removing the third insulation layer; and forming an ohmic electrode using a lift-off process.
摘要翻译：公开了一种制造金属半导体场效应晶体管的方法，包括以下步骤：使用离子注入形成沟道，顺序地形成第一预定温度的第一绝缘体层和在表面上的第二预定温度的第二绝缘层使用光致抗蚀剂图案的栅极图案蚀刻第一绝缘层和第二绝缘层以暴露沟道区域作为掩模，在第一和第二绝缘层的表面上形成耐火金属添加暴露的沟道区，蚀刻耐火金属，从而将其分成两部分，其中一部分形成在沟道区上，另一部分形成在第二绝缘层上，选择性地蚀刻第一绝缘层和第二绝缘层以在第一绝缘层上剥离难熔金属，第二绝缘层，从而在沟道区上形成T形栅极，使用ga将Si离子注入衬底和形成自对准高浓度离子注入区的通道图案，形成用于防止As蒸发的第三绝缘层，进行激活的快速热退火，去除第三绝缘层; 并使用剥离工艺形成欧姆电极。

55. 发明授权

US5314833A Method of manufacturing GaAs metal semiconductor field effect transistor 失效
标题翻译：制造GaAs金属半导体场效应晶体管的方法
公开(公告)号：US5314833A
公开(公告)日：1994-05-24
申请号：US996052
申请日：1992-12-23
申请人： Kyung-Ho Lee , Kyoung-Ik Cho , Yong-Tak Lee
发明人： Kyung-Ho Lee , Kyoung-Ik Cho , Yong-Tak Lee
IPC分类号： H01L29/812 , H01L21/22 , H01L21/225 , H01L21/265 , H01L21/338
CPC分类号： H01L29/66871 , H01L21/2258 , H01L21/2654 , H01L21/26553 , H01L21/2656
摘要： A method of manufacturing a GaAs field effect transistor comprises depositing a silicon thin film 202 on a semi-insulating semiconductor substrate 201, forming a first sensitive film 203 by a photolithography to define channel areas and ion-implanting n-type dopants into the substrate to form an activation layer, removing the first sensitive film, forming a second sensitive film 203a on the silicon thin film by photolithography to define an ohmic contact area and then forming a highly doped impurity layer on the side of the activation layer by way of an ion-implantation process, depositing a passivation film 206 over the entire surface of the substrate 201 after the removal of the sensitive film, and effecting an annealing or heat treatment, forming a third sensitive film of a predetermined pattern by using an ohmic contact forming mask, effecting a recess etching process to the surface of the substrate and forming an ohmic contact on the etched portion, and patterning a gate region by using the gate forming mask, recess-etching the surface of the substrate and depositing a low resistivity metal to form a gate.
摘要翻译：制造GaAs场效应晶体管的方法包括在半绝缘半导体衬底201上沉积硅薄膜202，通过光刻法形成第一敏感膜203，以将沟道区域和离子注入n型掺杂剂定义到衬底中形成激活层，去除第一敏感膜，通过光刻在硅薄膜上形成第二敏感膜203a以限定欧姆接触面积，然后通过离子在激活层侧上形成高度掺杂的杂质层在移除敏感膜之后，在衬底201的整个表面上沉积钝化膜206，进行退火或热处理，通过使用欧姆接触形成掩模形成预定图案的第三感光膜，对衬底的表面进行凹陷蚀刻工艺，并在蚀刻部分上形成欧姆接触，并且通过栅极区域图案化使用栅极形成掩模，凹陷蚀刻衬底的表面并沉积低电阻率金属以形成栅极。

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