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51. 发明申请

US20120293132A1 REMAINING CAPACITY CALCULATION METHOD, BATTERY PACK PRE-SHIPMENT ADJUSTMENT METHOD, REMAINING CAPACITY CALCULATING DEVICE AND BATTERY PACK 审中-公开
标题翻译：剩余容量计算方法，电池组预装置调整方法，剩余容量计算装置和电池组
公开(公告)号：US20120293132A1
公开(公告)日：2012-11-22
申请号：US13468306
申请日：2012-05-10
申请人： Tomomi KAINO , Naofumi Enomoto , Atsushi Kawasumi
发明人： Tomomi KAINO , Naofumi Enomoto , Atsushi Kawasumi
IPC分类号： H02J7/00
CPC分类号： H01M10/48 , G01R31/3835 , H01M10/4257 , H01M10/44 , H01M2010/4271 , H01M2010/4278
摘要： A MOSFET 61 is connected between a power supply IC6 and a 3.3-V power supply terminal. When the MOSFET 61 is turned OFF, a control circuit board 100 is shut down which includes a control portion 5 for calculating RSOC (remaining capacity ratio). When the control circuit board 100 returns from shutdown, the maximum cell voltage is detected as OCV (open circuit voltage). RSOC can be calculated based on the maximum cell voltage by using the discharge characteristic which relates OCV to RSOC. In this case, a quadratic curve line segment is selected from an approximate curve line which approximates the discharge characteristics. RSOC can be calculated by substituting the detected maximum cell voltage into the quadratic function which is represented by the selected quadratic curve line segment.
摘要翻译： MOSFET 61连接在电源IC6和3.3V电源端子之间。当MOSFET61断开时，关闭控制电路板100，该控制电路板100包括用于计算RSOC（剩余容量比）的控制部分5。当控制电路板100从关机返回时，将最大电池电压检测为OCV（开路电压）。可以通过使用将OCV与RSOC相关联的放电特性，基于最大电池电压来计算RSOC。在这种情况下，从近似放电特性的近似曲线中选择二次曲线段。可以通过将检测到的最大电池电压代入由所选择的二次曲线线段表示的二次函数来计算RSOC。

52. 发明申请

US20120243287A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IMPROVING DISTURBABILITY AND WRITABILITY 审中-公开
标题翻译：可提高可靠性和可写性的半导体存储器件
公开(公告)号：US20120243287A1
公开(公告)日：2012-09-27
申请号：US13244235
申请日：2011-09-23
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C5/06
CPC分类号： G11C11/413 , G11C11/412
摘要： According to one embodiment, a semiconductor memory device includes memory cells and sense amplifiers. Each of the memory cells comprises a flip-flop circuit and first to fourth transistors. The flip-flop circuit includes a first storage node and a second storage node. The first and second transistors are connected between the first and second storage nodes of the flip-flop circuit and the first and second bit lines, respectively, and have gate electrodes are connected to the word line. The third and fourth transistors have gate electrodes connected to the word line and disconnect a feedback loop of the flip-flop circuit when the first and second transistors are selected. In data write, of a plurality of sense amplifiers, a sense amplifier including an unselected memory cell which is connected to the word line writes back data output from the unselected memory cell to the unselected memory cell.
摘要翻译：根据一个实施例，半导体存储器件包括存储单元和读出放大器。每个存储单元包括触发器电路和第一至第四晶体管。触发器电路包括第一存储节点和第二存储节点。第一和第二晶体管分别连接在触发器电路的第一和第二存储节点以及第一和第二位线之间，并且栅电极连接到字线。当选择第一和第二晶体管时，第三和第四晶体管具有连接到字线的栅电极并断开触发器电路的反馈环路。在数据写入中，在多个读出放大器中，包括连接到字线的未选择的存储单元的读出放大器将从未选择的存储单元输出的数据写回到未选择的存储单元。

53. 发明授权

US08107278B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08107278B2
公开(公告)日：2012-01-31
申请号：US12328637
申请日：2008-12-04
申请人： Takahiko Sasaki , Atsushi Kawasumi
发明人： Takahiko Sasaki , Atsushi Kawasumi
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C7/18 , G11C5/025 , G11C11/412 , G11C11/413
摘要： A semiconductor storage device includes a memory cell array having a plurality of SRAM cells arranged along a pair of bit lines that extend along a first direction. A read circuit is arranged for each column at one side of the memory cell array and detects a potential of any one of the pair of bit lines. A write circuit is arranged, separately from the read circuit, at the other side of the memory cell array. The write circuit provides written data to the pair of bit lines to write data to the SRAM cells.
摘要翻译：半导体存储装置包括具有沿着沿第一方向延伸的一对位线布置的多个SRAM单元的存储单元阵列。为存储单元阵列的一侧的每列配置读取电路，并且检测该对位线中的任何一个的电位。写入电路与读取电路分离地布置在存储单元阵列的另一侧。写电路将写数据提供给该对位线，以将数据写入SRAM单元。

54. 发明授权

US08018757B2 Semiconductor memory device and trimming method thereof 有权
标题翻译：半导体存储器件及其修整方法
公开(公告)号：US08018757B2
公开(公告)日：2011-09-13
申请号：US12539883
申请日：2009-08-12
申请人： Atsushi Kawasumi , Yukihiro Urakawa
发明人： Atsushi Kawasumi , Yukihiro Urakawa
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C5/147 , G11C11/41 , G11C11/413 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/50 , G11C2207/2254
摘要： The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. When offset information of the memory cell is to be read, a voltage applied to the first power supply terminal and a voltage applied to the second power supply terminal are made equal. Then the voltage applied to the first power supply terminal is returned to the first potential, and the voltage applied to the second power supply terminal is returned to the second potential. When stress is generated in the first to fourth transistor included in the first or second inverter, the potential difference between the first power supply terminal and the second power supply terminal is made larger than a difference between the first potential and the second potential.
摘要翻译：第一电源端子连接到第一和第三晶体管的源电极。第二电源端子连接到第二和第四晶体管的源电极。当要读取存储器单元的偏移信息时，施加到第一电源端子的电压和施加到第二电源端子的电压相等。然后，施加到第一电源端子的电压返回到第一电位，并且施加到第二电源端子的电压返回到第二电位。当在包括在第一或第二逆变器中的第一至第四晶体管中产生应力时，使得第一电源端子和第二电源端子之间的电位差大于第一电位和第二电位之间的差。

55. 发明申请

US20100213891A1 BATTERY PACK UPDATING METHOD 有权
标题翻译：电池组更新方法
公开(公告)号：US20100213891A1
公开(公告)日：2010-08-26
申请号：US12707139
申请日：2010-02-17
申请人： Toru Nishikawa , Atsushi Kawasumi
发明人： Toru Nishikawa , Atsushi Kawasumi
IPC分类号： H02J7/00
CPC分类号： H01M10/42 , H01M10/052 , H01M10/48 , H02J7/02 , H02J2007/0098
摘要： The battery pack updating method updates firmware stored in internal control circuit memory 24 via an update signal sent from a main device 1 that supplies power. When battery pack memory is updated, an AC adapter 3 is connected to the main device, and power is supplied to the main device from the AC adapter. The updating method transmits a charging and discharging blocking signal from the main device to the battery pack 2 control circuit 21 via a communication line 19. The charging and discharging blocking signal stops discharge from the battery pack 2 rechargeable battery 20, and stops charging of the rechargeable battery 20. With rechargeable battery 20 discharging and charging to and from the main device stopped by the charging and discharging blocking signal, the updating method transmits update data from the main device to the battery pack 2 control circuit 21 to update memory 24.
摘要翻译：电池组更新方法通过从供给电力的主装置1发送的更新信号来更新存储在内部控制电路存储器24中的固件。当更换电池组存储器时，将AC适配器3连接到主设备，并从AC适配器向主设备供电。更新方法通过通信线路19将主装置的充放电阻断信号发送到电池组2的控制电路21.充放电阻断信号停止从电池组2的可再充电电池20的放电，并停止充电可再充电电池20.随着充电电池20对通过充放电阻断信号停止的主设备进行放电和充电，更新方法将更新数据从主设备发送到电池组2控制电路21以更新存储器24。

56. 发明授权

US07675263B2 Method for controlling battery pack 有权
标题翻译：电池组控制方法
公开(公告)号：US07675263B2
公开(公告)日：2010-03-09
申请号：US11703172
申请日：2007-02-07
申请人： Atsushi Kawasumi , Toru Nishikawa
发明人： Atsushi Kawasumi , Toru Nishikawa
IPC分类号： H02J7/00 , F21L4/00 , H01M2/10 , H04M1/00
CPC分类号： H02H7/18 , H01M2/34 , H01M2/348 , H02H3/023 , H02J7/0031
摘要： A battery pack includes a switching element, a heat resistor, and a fuse. The switching element turns to ON if the battery pack becomes in an abnormal state. The heat resistor is connected to the switching element and a battery in series. Current flows through the heat resistor when the switching element turns to ON. The fuse is located in a position where the fuse is heated by the heat resistor through which the current flows. The fuse is connected to the battery in series so that the fuse is disconnected with heat by the heat resistor at high temperature. Thus, the fuse cuts off a current flow in the battery. If the battery pack is in an abnormal state, when the capacity or voltage of the battery is less than a preset capacity or voltage value, the fuse is disconnected with heat by turning the switching element to ON.
摘要翻译：电池组包括开关元件，热电阻器和保险丝。如果电池组处于异常状态，则开关元件变为ON。热电阻器与开关元件和电池串联连接。当开关元件变为ON时，电流流经热电阻。保险丝位于熔断器被电流流过的热电阻加热的位置。保险丝串联连接到电池，使得保险丝在高温下被热电阻器的热量断开。因此，熔丝切断电池中的电流。如果电池组处于异常状态，当电池的容量或电压小于预设容量或电压值时，通过将开关元件转为ON，保险丝断开。

57. 发明授权

US07558924B2 Systems and methods for accessing memory cells 失效
标题翻译：访问存储单元的系统和方法
公开(公告)号：US07558924B2
公开(公告)日：2009-07-07
申请号：US11047502
申请日：2005-01-31
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G06F13/00
CPC分类号： G11C11/413 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/22
摘要： Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a memory system includes an array of a first type of memory cells and a register having cells of a second type. The second type of cells is designed to stabilize data more quickly than the first type. Data is written concurrently into the memory array and the register. When a read operation is directed to the location of an immediately preceding write operation, the data is read from the register. When a read operation is directed to a location that is not coincident with an immediately preceding write operation, the data is read from the memory array.
摘要翻译：用于访问存储器中的数据的系统和方法，其中提供寄存器以临时存储来自写入操作的数据，并使数据可用于在写入操作之后立即执行并且被引导到相同数据的读取操作。在一个实施例中，存储器系统包括第一类型存储器单元的阵列和具有第二类型的单元的寄存器。第二种类型的电池被设计为比第一类更稳定数据。数据同时写入存储器阵列和寄存器。当读取操作指向紧接在前的写入操作的位置时，从寄存器读取数据。当读取操作指向与紧接在前的写入操作不一致的位置时，从存储器阵列中读取数据。

58. 发明申请

US20090153104A1 Charging method 失效
标题翻译：充电方式
公开(公告)号：US20090153104A1
公开(公告)日：2009-06-18
申请号：US12314483
申请日：2008-12-11
申请人： Shinichi Matsuura , Atsushi Kawasumi
发明人： Shinichi Matsuura , Atsushi Kawasumi
IPC分类号： H02J7/04
CPC分类号： H02J7/0091
摘要： A charging method includes first and second charging steps to charge a lithium-ion battery. In the first charging step, a temperature rise gradient of the battery to a current is detected. A battery temperature when the battery is charged to a first predetermined capacity is predicted based on the gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that brings a battery temperature lower than a predetermined temperature, to the first predetermined capacity. In the second charging step, a temperature rise gradient of the battery is detected. A battery temperature when the battery is charged to a second predetermined capacity is predicted based on the gradient. A charging current is controlled based on the predicted temperature. The battery is charged, at a current that brings the temperature of the battery lower than the predetermined temperature, to the second predetermined capacity.
摘要翻译：充电方法包括对锂离子电池充电的第一和第二充电步骤。在第一充电步骤中，检测电池对电流的升温梯度。基于该梯度来预测电池充电到第一预定容量时的电池温度。充电电流根据预测温度进行控制。在电池温度低于预定温度的电流下将电池充电到第一预定容量。在第二充电步骤中，检测电池的升温梯度。基于该梯度来预测将电池充电到第二预定容量时的电池温度。充电电流根据预测温度进行控制。在将电池的温度低于预定温度的电流下将电池充电到第二预定容量。

59. 发明申请

US20080094125A1 Semiconductor integrated circuit device and semiconductor device including plurality of semiconductor circuits 失效
标题翻译：半导体集成电路器件和包括多个半导体电路的半导体器件
公开(公告)号：US20080094125A1
公开(公告)日：2008-04-24
申请号：US11975470
申请日：2007-10-19
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： H03K3/01
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit device includes a first semiconductor circuit, a second semiconductor circuit, a first control circuit and a second control circuit. The first and second semiconductor circuits are formed on a semiconductor substrate and operate using a voltage provided by an external power supply circuit as a power supply voltage. The first control circuit is formed on the semiconductor substrate and holds control information used to control the voltage generated by the external power supply circuit in accordance with operating performance of the first and second semiconductor circuits. The second control circuit controls a property of the first semiconductor circuit in accordance with the control information held by the first control circuit.
摘要翻译：半导体集成电路器件包括第一半导体电路，第二半导体电路，第一控制电路和第二控制电路。第一和第二半导体电路形成在半导体衬底上，并且使用由外部电源电路提供的电压作为电源电压进行操作。第一控制电路形成在半导体衬底上，并且保持用于根据第一和第二半导体电路的操作性能来控制由外部电源电路产生的电压的控制信息。第二控制电路根据由第一控制电路保持的控制信息控制第一半导体电路的特性。

60. 发明申请

US20060171190A1 Systems and methods for accessing memory cells 失效
公开(公告)号：US20060171190A1
公开(公告)日：2006-08-03
申请号：US11047502
申请日：2005-01-31
申请人： Atsushi Kawasumi
发明人： Atsushi Kawasumi
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/106 , G11C7/22
摘要： Systems and methods for accessing data in a memory, where a register is provided to temporarily store data from a write operation and to make the data available for read operations that are performed immediately following the write operation and are directed to the same data. In one embodiment, a memory system includes an array of a first type of memory cells and a register having cells of a second type. The second type of cells is designed to stabilize data more quickly than the first type. Data is written concurrently into the memory array and the register. When a read operation is directed to the location of an immediately preceding write operation, the data is read from the register. When a read operation is directed to a location that is not coincident with an immediately preceding write operation, the data is read from the memory array.

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