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51. 发明授权

US07814166B2 Methods and apparatus for virtualizing an address space 有权
标题翻译：用于虚拟化地址空间的方法和装置
公开(公告)号：US07814166B2
公开(公告)日：2010-10-12
申请号：US11341724
申请日：2006-01-27
申请人： Masakazu Suzuoki
发明人： Masakazu Suzuoki
IPC分类号： G06F15/16
CPC分类号： H04L67/1097 , G06F12/0833 , G06F12/1081
摘要： Methods and apparatus provide for: receiving a memory access request for data from a processor of a multi-processor system; determining whether the data of the memory access request is stored in a remote processing system coupled to the multi-processor system over a communications network; requesting the data from the remote processing system; receiving the data from the remote processing system over the communications network; and providing the data to the processor of the multi-processor system.
摘要翻译：方法和装置提供：从多处理器系统的处理器接收对数据的存储器访问请求; 确定所述存储器访问请求的数据是否存储在通过通信网络耦合到所述多处理器系统的远程处理系统中; 从远程处理系统请求数据; 通过通信网络从远程处理系统接收数据; 以及将数据提供给多处理器系统的处理器。

52. 发明授权

US07720982B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07720982B2
公开(公告)日：2010-05-18
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

53. 发明授权

US07516334B2 Power management for processing modules 有权
标题翻译：处理环境中的电源管理
公开(公告)号：US07516334B2
公开(公告)日：2009-04-07
申请号：US10959700
申请日：2004-10-05
申请人： Masakazu Suzuoki , Takeshi Yamazaki
发明人： Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/3243 , G06F9/30145 , G06F9/30167 , Y02D10/152 , Y02D10/16
摘要： A processing element (PE) includes a processing unit (PU) and a number of attached processing units (APUs). The instruction set of each APU is divided a priori into a number of types, each type associated with a different amount of heat generation. Each APU keeps track of the amount of each type of instruction executed over a time period, —the power information, —and provides this power information to the PU. The PU then performs power management as a function of the provided power information from each APU, —such as directing a particular APU to enter an idle state to reduce power consumption.
摘要翻译：处理单元（PE）包括处理单元（PU）和多个附加处理单元（APU）。每个APU的指令集被预先划分成多种类型，每种类型与不同的发热量相关联。每个APU跟踪在一段时间内执行的每种类型的指令的数量 - 功率信息，并将该功率信息提供给PU。然后，PU根据来自每个APU的所提供的功率信息执行功率管理，例如指示特定APU进入空闲状态以降低功耗。

54. 发明授权

US07475257B2 System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data 有权
标题翻译：用于在多处理器系统中选择和使用信号处理器以用作数据的加密/解密的安全性的系统和方法
公开(公告)号：US07475257B2
公开(公告)日：2009-01-06
申请号：US10670825
申请日：2003-09-25
申请人： Maximino Aguilar, Jr. , David Craft , Michael Norman Day , Akiyuki Hatakeyama , Harm Peter Hofstee , Masakazu Suzuoki
发明人： Maximino Aguilar, Jr. , David Craft , Michael Norman Day , Akiyuki Hatakeyama , Harm Peter Hofstee , Masakazu Suzuoki
IPC分类号： H04L9/32
CPC分类号： G06F21/6236 , G06F21/602 , H04L9/0894 , H04L2209/125
摘要： A system and method are provided to dedicate one or more processors in a multiprocessing system to performing encryption functions. When the system initializes, one of the synergistic processing unit (SPU) processors is configured to run in a secure mode wherein the local memory included with the dedicated SPU is not shared with the other processors. One or more encryption keys are stored in the local memory during initialization. During initialization, the SPUs receive nonvolatile data, such as the encryption keys, from nonvolatile register space. This information is made available to the SPU during initialization before the SPUs local storage might be mapped to a common memory map. In one embodiment, the mapping is performed by another processing unit (PU) that maps the shared SPUs' local storage to a common memory map.
摘要翻译：提供了一种系统和方法来将多处理系统中的一个或多个处理器专用于执行加密功能。当系统初始化时，协同处理单元（SPU）中的一个处理器被配置为以安全模式运行，其中包括在专用SPU中的本地存储器不与其他处理器共享。在初始化期间，一个或多个加密密钥存储在本地存储器中。在初始化期间，SPU从非易失性寄存器空间接收非易失性数据，例如加密密钥。在SPU本地存储可能映射到公共存储器映射之前，该信息在初始化期间可用于SPU。在一个实施例中，映射由将共享的SPU本地存储映射到公共存储器映射的另一个处理单元（PU）执行。

55. 发明授权

US07038676B2 System and method for data compression 有权
公开(公告)号：US07038676B2
公开(公告)日：2006-05-02
申请号：US10167328
申请日：2002-06-11
申请人： Eiji Iwata , Masakazu Suzuoki
发明人： Eiji Iwata , Masakazu Suzuoki
IPC分类号： G06F17/00 , G09G5/00 , G06T13/00
CPC分类号： H04N19/51 , G06T9/001 , H04N19/20 , H04N19/57
摘要： A system and method for compressing video graphics data are provided. The system and method include generating in a graphics pipeline, from video graphics data modeling objects, vertex data corresponding to the objects, rendering the video graphics data to produce a current frame of pixel data and a reference frame of pixel data, and, based upon the vertex data, defining a search area within the reference frame for calculating a motion vector for a block of pixel data within the current frame. The current frame then is compressed using the motion vector. The use of vertex data from the graphics pipeline to define the search area substantially reduces the amount of searching necessary to generate motion vectors and perform data compression.

56. 发明申请

US20050081213A1 System and method for data synchronization for a computer architecture for broadband networks 有权
标题翻译：宽带网络计算机架构的数据同步系统和方法
公开(公告)号：US20050081213A1
公开(公告)日：2005-04-14
申请号：US10967362
申请日：2004-10-18
申请人： Masakazu Suzuoki , Takeshi Yamazaki
发明人： Masakazu Suzuoki , Takeshi Yamazaki
IPC分类号： G06F12/14 , G06F15/16 , G06F15/80 , G06F21/24 , H04L29/06 , G06F9/46
CPC分类号： G06F12/1466 , H04L69/12
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing tasks is also provided. The processing system includes processing devices and an absolute timer. The absolute timer defines a time budget. The time budget provides a time period for the completion of tasks by selected processing devices independent of clock frequencies employed by the processing devices for processing the tasks.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。还提供了一种用于处理任务的处理系统。处理系统包括处理设备和绝对定时器。绝对计时器定义时间预算。时间预算为选择的处理设备完成任务提供了一个时间段，独立于处理设备处理任务使用的时钟频率。

57. 发明授权

US06563999B1 Method and apparatus for information processing in which image data is displayed during loading of program data, and a computer readable medium and authoring system therefor 失效
标题翻译：用于信息处理的方法和装置，其中在加载节目数据期间显示图像数据，以及计算机可读介质及其创作系统
公开(公告)号：US06563999B1
公开(公告)日：2003-05-13
申请号：US09047711
申请日：1998-03-25
申请人： Masakazu Suzuoki
发明人： Masakazu Suzuoki
IPC分类号： H04N576
CPC分类号： G06F9/445 , A63F13/10 , A63F13/95 , A63F2300/207 , G11B27/034 , G11B27/105 , G11B2220/20 , H04N5/781 , H04N5/85 , H04N9/8042 , H04N9/8205 , H04N21/4325 , H04N2005/91335
摘要： Data sequentially read from a storage device, such as a CD-ROM, in which program data and moving picture data are alternately recorded, is divided into program data and moving picture data by a demultiplexor. The moving picture data is stored in an image data storage region of a main memory. The moving picture data is then expanded by an MPEG decoder and is transferred to a decoded image buffer, and is further transferred to a frame memory of a graphic processing unit. Every time moving picture data for one frame is transferred to the frame memory, it is converted into a video signal and output. Accordingly, the loading time for the program data is decreased even though the moving picture data is reproduced while the program data is being loaded.
摘要翻译：从程序数据和运动图像数据被交替记录的诸如CD-ROM的存储装置顺序地读取的数据被解复用器分成程序数据和运动图像数据。运动图像数据被存储在主存储器的图像数据存储区域中。运动图像数据然后被MPEG解码器扩展并被传送到解码图像缓冲器，并进一步传送到图形处理单元的帧存储器。每当一帧的运动图像数据被传送到帧存储器时，它被转换成视频信号并输出。因此，即使在程序数据被加载时再现运动图像数据，也减少了程序数据的加载时间。

58. 发明授权

US06219073B1 Apparatus and method for information processing using list with embedded instructions for controlling data transfers between parallel processing units 失效
标题翻译：用于使用具有用于控制并行处理单元之间的数据传输的嵌入式指令的列表的信息处理的装置和方法
公开(公告)号：US06219073B1
公开(公告)日：2001-04-17
申请号：US09048137
申请日：1998-03-25
申请人： Masakazu Suzuoki
发明人： Masakazu Suzuoki
IPC分类号： G06F1300
CPC分类号： G06T1/20
摘要： In a data processing apparatus, data is transferred in accordance with a meta-instruction embedded in the data. To put it in detail, first of all, a first meta-instruction is read out from an address ADDR0 stored in a tag address register Dn_TADR. Then, data following the first meta-instruction with a length specified by the meta-instruction is transferred. Subsequently, a second meta-instruction stored at an address ADDR2 specified in the first meta-instruction is read out and data following the second meta-instruction with a length specified by the second meta-instruction is transferred. A third next meta-instruction stored at an address ADDR1 specified in the second meta-instruction is further read out and data following the third meta-instruction with a length specified by the third meta-instruction is then transferred.
摘要翻译：在数据处理装置中，根据嵌入在数据中的元指令传送数据。为了详细说明，首先，从存储在标签地址寄存器Dn_TADR中的地址ADDR0中读出第一元指令。然后，传送由元指令指定的长度的第一元指令之后的数据。随后，读出存储在第一元指令中指定的地址ADDR2处的第二元指令，并传送第二元指令之后的数据，该第二元指令具有由第二元指令指定的长度。存储在第二元指令中指定的地址ADDR1处的第三个下一个元指令被进一步读出，然后传送具有由第三元指令指定的长度的第三元指令之后的数据。

59. 发明授权

US06188408B1 Methods and apparatus for recording and information processing, and recording method therefor 失效
标题翻译：用于记录和信息处理的方法和装置及其记录方法
公开(公告)号：US06188408B1
公开(公告)日：2001-02-13
申请号：US08853705
申请日：1997-05-09
申请人： Masakazu Suzuoki
发明人： Masakazu Suzuoki
IPC分类号： G06T1720
CPC分类号： G06T17/20
摘要： A recording medium, recording and information processing apparatus and methods by which efficient processing of data and a high processing speed can be readily achieved at lower cost. A main CPU converts coordinates of a polygon in response to a manual operation of an operation unit by a user and transmits data of the polygon to a programmable packet engine via a main bus. The packet engine calculates a Z value representative of the position of the polygon in the depthwise direction from coordinate values of the apexes of the polygon supplied from the main CPU, divides the polygon into a number of sub-polygons corresponding to the Z value, converts coordinate values of the apexes of the sub-polygons in accordance with a normal vector and curved surface parameters and produces a curved surface composed of the sub-polygons. A graphical processing unit writes pixel data of the sub-polygons produced by the programmable packet engine into a frame buffer and performs rendering processing.
摘要翻译：记录介质，记录和信息处理设备以及以较低的成本容易地实现数据的有效处理和高处理速度的方法。主CPU响应于用户对操作单元的手动操作而转换多边形的坐标，并且经由主总线将多边形的数据发送到可编程分组引擎。分组引擎从主CPU提供的多边形的顶点的坐标值计算代表多边形在深度方向上的位置的Z值，将多边形分割成与Z值对应的子多边形数，转换根据法向量和曲面参数对子多边形的顶点进行坐标值，并产生由子多边形组成的曲面。图形处理单元将由可编程分组引擎产生的子多边形的像素数据写入帧缓冲器并执行绘制处理。

60. 发明授权

US5774125A Texture mapping method in which 3-D image data is transformed into 2-D data and mapped onto a surface of an object for display 失效
标题翻译：纹理映射方法，其中将3-D图像数据变换成2-D数据并映射到要显示的对象的表面上
公开(公告)号：US5774125A
公开(公告)日：1998-06-30
申请号：US611624
申请日：1996-03-06
申请人： Masakazu Suzuoki , Makoto Furuhashi
发明人： Masakazu Suzuoki , Makoto Furuhashi
IPC分类号： G06T15/04 , G06T15/00
CPC分类号： G06T15/04
摘要： A real time texture mapping method produces an image of an object having a surface that has dynamically changing texture by using image data and moving image texture pattern data. The image data is stored in a drawing area of an image memory, and the moving image texture pattern data is stored frame-by-frame in a texture area of the image memory. The moving image texture pattern data stored in the texture area is mapped a frame per vertical display period onto the surface of the object which is represented in the image data stored in the drawing area. The new two-dimensional image data having the texture pattern data mapped on the surface of the object is used as a current image frame for display. The new image data having the texture pattern data mapped on the surface of the object may be stored in the texture area of the image memory, and used as a new texture pattern to map onto a second object stored in the drawing area for a next image frame to be displayed. A video game apparatus implementing this method includes the image memory having a display area as well as the texture area and drawing area. The display area stores image data of the current image frame for display. The drawing and display areas have interchangeable functions.
摘要翻译：实时纹理映射方法通过使用图像数据和运动图像纹理图案数据产生具有具有动态变化纹理的表面的对象的图像。图像数据被存储在图像存储器的绘图区域中，并且运动图像纹理图案数据被逐帧地存储在图像存储器的纹理区域中。存储在纹理区域中的运动图像纹理图案数据被映射到每个垂直显示周期的帧到存储在绘图区域中的图像数据中表示的对象的表面上。将具有映射在物体表面上的纹理图案数据的新的二维图像数据用作当前显示图像帧。具有映射在对象表面上的纹理图案数据的新图像数据可以存储在图像存储器的纹理区域中，并且用作新的纹理图案以映射到存储在绘图区域中的下一个图像的第二对象框架显示。实现该方法的视频游戏装置包括具有显示区域以及纹理区域和绘图区域的图像存储器。显示区域存储用于显示的当前图像帧的图像数据。绘图和显示区域具有可互换的功能。

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