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51. 发明授权

US09116432B2 Multiple exposure with image reversal in a single photoresist layer 有权
标题翻译：在单一光致抗蚀剂层中具有图像反转的多次曝光
公开(公告)号：US09116432B2
公开(公告)日：2015-08-25
申请号：US13814356
申请日：2011-08-09
申请人： Coumba Ndoye , Marius Orlowski
发明人： Coumba Ndoye , Marius Orlowski
IPC分类号： G03F7/20 , H01L21/027 , G03F7/095 , G03F7/26
CPC分类号： G03F7/2022 , G03F7/095 , G03F7/2024 , G03F7/203 , G03F7/26 , H01L21/0272 , H01L21/0274 , Y10T428/24802
摘要： Multiple patterned exposures of a single layer of image reversal resist prior to and following image reversal processing, upon development, respond to the respective exposures as either a positive or a negative resist, allowing a desired shape of a resist structure to be built up from any of a number of combinations of primitive masks. Exploiting the image reversal resist in this manner allows several types of diffraction distortion to be entirely avoided and for many sophisticated lithographic processes to he reduced in complexity by one-half or more while any desired resist structure shape can be formed form a limited number of primitive mask patterns. A regimen, which may be automated as an executable algorithm for a computer may be followed to evaluate different combinations of masks which are valid to produce a desired resist structure shape and select the optimum mask pattern combination to do so.
摘要翻译：在图像反转处理之前和之后的单层图像反转抗蚀剂的多个图案曝光在显影时，将各自的曝光作为正或负光刻胶响应，允许抗蚀剂结构的期望形状从任何的原始面具的多种组合。以这种方式利用图像反转抗蚀剂允许完全避免几种类型的衍射失真，并且对于许多复杂的光刻工艺，他将复杂度降低了一半以上，同时可以形成有限数量的原始形状的任何期望的抗蚀剂结构形状面具图案。可以遵循可以自动化作为计算机的可执行算法的方案，以评估有效产生期望的抗蚀剂结构形状并选择最佳掩模图案组合的掩模的不同组合。

52. 发明申请

US20120126413A1 METHOD OF SEALING AN AIR GAP IN A LAYER OF A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE 有权
标题翻译：在半导体结构和半导体结构层中密封空气隙的方法
公开(公告)号：US20120126413A1
公开(公告)日：2012-05-24
申请号：US13300953
申请日：2011-11-21
申请人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
发明人： Greg Braeckelmann , Marius Orlowski , Andreas Wild
IPC分类号： H01L23/48
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76834
摘要： Providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer. The air gap extends into the first layer from a first surface of the first layer. A barrier dielectric material over the first surface and the air gap is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. An air gap can extend from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces.
摘要翻译：提供在第一层中形成的导线之间具有至少一个气隙的半导体结构的第一层。气隙从第一层的第一表面延伸到第一层。选择第一表面和空气间隙上的阻挡介电材料以具有小于3.5的介电常数并提供屏障以防止化学品进入至少一个气隙。气隙可以从第一层的第一表面延伸到至少两个导电线的侧表面的至少一部分，以暴露侧表面的至少一部分。

53. 发明申请

US20110021036A1 METHOD OF SEALING AN AIR GAP IN A LAYER OF A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE 有权
标题翻译：在半导体结构和半导体结构层中密封空气隙的方法
公开(公告)号：US20110021036A1
公开(公告)日：2011-01-27
申请号：US12936113
申请日：2008-04-17
申请人： Greg Braecklmann , Marius Orlowski , Andreas Wild
发明人： Greg Braecklmann , Marius Orlowski , Andreas Wild
IPC分类号： H01L21/312
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76834
摘要： A method of sealing an air gap in a layer of a semiconductor structure comprises providing a first layer of the semiconductor structure having at least one air gap for providing isolation between at least two conductive lines formed in the first layer. The at least one air gap extends into the first layer from a first surface of the first layer. The method further comprises forming a barrier layer of a barrier dielectric material over the first surface of the first layer and the at least one air gap. The barrier dielectric material is selected to have a dielectric constant less than 3.5 and to provide a barrier to prevent chemicals entering the at least one air gap. In another embodiment, the at least one air gap extends from a first surface of the first layer to at least a portion of side surfaces of the at least two conductive lines to expose at least a portion of the side surfaces, and a barrier layer of a barrier dielectric material is formed over the exposed portions of the side surfaces of each of the at least two conductive lines.
摘要翻译：密封半导体结构层中的气隙的方法包括提供具有至少一个气隙的半导体结构的第一层，用于在形成在第一层中的至少两个导电线之间提供隔离。所述至少一个气隙从所述第一层的第一表面延伸到所述第一层中。该方法还包括在第一层的第一表面和至少一个气隙上形成阻挡介电材料的阻挡层。阻挡介电材料被选择为具有小于3.5的介电常数并且提供屏障以防止化学品进入至少一个气隙。在另一个实施例中，至少一个空气间隙从第一层的第一表面延伸到至少两个导电线的侧表面的至少一部分以暴露至少一部分侧表面，并且阻挡层在所述至少两根导电线中的每一个的侧表面的暴露部分上形成阻挡介电材料。

54. 发明申请

US20110003451A1 INTERMEDIATE PRODUCT FOR A MULTICHANNEL FET AND PROCESS FOR OBTAINING AN INTERMEDIATE PRODUCT 有权
标题翻译：用于多通道FET的中间产品和获得中间产品的过程
公开(公告)号：US20110003451A1
公开(公告)日：2011-01-06
申请号：US12865517
申请日：2008-02-08
申请人： Marius Orlowski , Andreas Wild
发明人： Marius Orlowski , Andreas Wild
IPC分类号： H01L21/336 , H01L29/165 , H01L21/20
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772 , H01L29/78687
摘要： An intermediate product in the manufacture of a vertical multiple-channel FET device containing alternating —Si—[(SiGe)—Si]u- stacked layers is shown, as well as a process for selectively etching the SiGe layers in such a stacked layer system, and products obtained from such selective etching. Differential Ge content is added to the successive layers to provide uniform removal of the sacrificial SiGe layers.
摘要翻译：示出了制造包含交替的-Si - [（SiGe）-Si]层叠层的垂直多通道FET器件的中间产品，以及用于在这种堆叠层系统中选择性蚀刻SiGe层的工艺，以及从这种选择性蚀刻获得的产品。将差分Ge含量添加到连续层中以提供牺牲SiGe层的均匀去除。

55. 发明申请

US20070212832A1 Method for making a multibit transistor 审中-公开
标题翻译：制造多位晶体管的方法
公开(公告)号：US20070212832A1
公开(公告)日：2007-09-13
申请号：US11370320
申请日：2006-03-08
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L29/7887 , H01L21/26586 , H01L29/40114 , H01L29/42332
摘要： A method for making a transistor (301) is provided. In accordance with the method, a semiconductor substrate (201, 203) is provided, and a gate stack is formed on the substrate. The gate stack comprises first (205), second (207), and third (209) dielectric layers, wherein the second dielectric layer is disposed between said first and said third dielectric layers. A lateral recess (213) is then created in the second dielectric layer, and a charge storage material (215) is deposited in the lateral recess.
摘要翻译：提供一种制造晶体管（301）的方法。根据该方法，提供半导体衬底（201,203），并且在衬底上形成栅叠层。栅极堆叠包括第一（205），第二（207）和第三（209）电介质层，其中第二介电层设置在所述第一和第三介电层之间。然后在第二电介质层中形成横向凹槽（213），并且电荷存储材料（215）沉积在横向凹槽中。

56. 发明申请

US20070210338A1 Charge storage structure formation in transistor with vertical channel region 有权
标题翻译：具有垂直沟道区的晶体管中的电荷存储结构形成
公开(公告)号：US20070210338A1
公开(公告)日：2007-09-13
申请号：US11370283
申请日：2006-03-08
申请人： Marius Orlowski
发明人： Marius Orlowski
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7887 , H01L29/7926
摘要： A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.
摘要翻译：半导体器件包括具有第一侧壁的半导体结构。沿着第一侧壁在第一电流电极区域和第二电流电极区域之间的半导体结构中形成垂直沟道区域。第一和第二电荷存储结构在电介质层的开口中与第一侧壁相邻形成。第一和第二电荷存储结构彼此和半导体结构电隔离。控制电极与第一侧壁相邻地形成。在另一个实施例中，第三和第四电荷存储结构可以在电介质层的开口中邻近半导体结构的第二侧壁形成。

57. 发明申请

US20070176227A1 MOS device with nano-crystal gate structure 有权
标题翻译：具有纳米晶体栅结构的MOS器件
公开(公告)号：US20070176227A1
公开(公告)日：2007-08-02
申请号：US11343624
申请日：2006-01-30
申请人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
发明人： Chun-Li Liu , Tushar Merchant , Marius Orlowski , Matthew Stoker
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/7883 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/66825 , H01L29/78
摘要： Methods and apparatus are provided for non-volatile semiconductor devices. The apparatus comprises a substrate having therein a source region and a drain region separated by a channel region extending to a first surface of the substrate, and a multilayered gate structure containing nano-crystals located above the channel region. The gate structure comprises, a gate dielectric substantially in contact with the channel region, spaced-apart nano-crystals disposed in the gate dielectric, one or more impurity blocking layers overlying the gate dielectric and a gate conductor layer overlying the one more impurity blocking layers. The blocking layer nearest the gate conductor can also be used to adjust the threshold voltage of the device and/or retard dopant out-diffusion from the gate conductor layer.
摘要翻译：为非易失性半导体器件提供了方法和装置。该装置包括其中具有源极区域和漏极区域的衬底，漏极区域被延伸到衬底的第一表面的沟道区域分开，以及包含位于沟道区域上方的纳米晶体的多层栅极结构。栅极结构包括：基本上与沟道区接触的栅极电介质，设置在栅极电介质中的间隔开的纳米晶体，覆盖栅极电介质的一个或多个杂质阻挡层和覆盖一个以上杂质阻挡层的栅极导体层。最靠近栅极导体的阻挡层也可用于调节器件的阈值电压和/或从栅极导体层延迟掺杂剂扩散。

58. 发明申请

US20070148894A1 SEMICONDUCTOR DEVICE AND METHOD FOR REGIONAL STRESS CONTROL 审中-公开
标题翻译：用于区域应力控制的半导体器件和方法
公开(公告)号：US20070148894A1
公开(公告)日：2007-06-28
申请号：US11682579
申请日：2007-03-06
申请人： Marius Orlowski , Vance Adams
发明人： Marius Orlowski , Vance Adams
IPC分类号： H01L21/331
CPC分类号： H01L27/1203 , H01L21/84 , H01L21/86 , H01L29/7846
摘要： Mechanical stress control may be achieved using materials having selected elastic moduli. These materials may be selectively formed by implantation, may be provided as a plurality of buried layers interposed between the substrate and the active area, and may be formed by replacing selected portions of one or more buried layers. Any one or more of these methods may be used in combination. Mechanical stress control may be useful in the channel region of a semiconductor device to maximize its performance. In addition, these same techniques and structures may be used for other purposes besides mechanical stress control.
摘要翻译：可以使用具有选定的弹性模量的材料实现机械应力控制。这些材料可以通过注入选择性地形成，可以设置为插入在基板和有源区域之间的多个掩埋层，并且可以通过替换一个或多个掩埋层的选定部分来形成。这些方法中的任何一种或多种可以组合使用。机械应力控制在半导体器件的通道区域中可能是有用的，以使其性能最大化。此外，除了机械应力控制之外，这些相同的技术和结构可以用于其它目的。

59. 发明申请

US20070082431A1 Programmable fuse with silicon germanium 有权
标题翻译：可编程熔丝与硅锗
公开(公告)号：US20070082431A1
公开(公告)日：2007-04-12
申请号：US11247479
申请日：2005-10-11
申请人： Alexander Hoefler , Marius Orlowski
发明人： Alexander Hoefler , Marius Orlowski
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A programmable fuse and method of formation utilizing a layer of silicon germanium (SiGe) (e.g. monocrystalline) as a thermal insulator to contain heat generated during programming. The programmable fuse, in some examples, may be devoid of any dielectric materials between a conductive layer and a substrate. In one example, the conductive layer serves as programmable material, that in a low impedance state, electrically couples conductive structures. A programming current is applied to the programmable material to modify the programmable material to place the fuse in a high impedance state.
摘要翻译：一种可编程保险丝和利用硅锗层（SiGe）（例如单晶）作为热绝缘体的层的形成方法，以包含编程期间产生的热。在一些示例中，可编程熔丝可以在导电层和衬底之间没有任何介电材料。在一个示例中，导电层用作可编程材料，其在低阻抗状态下电耦合导电结构。将编程电流施加到可编程材料以修改可编程材料以将熔丝置于高阻抗状态。

60. 发明申请

US20070001162A1 Single transistor memory cell with reduced programming voltages 有权
公开(公告)号：US20070001162A1
公开(公告)日：2007-01-04
申请号：US11172570
申请日：2005-06-30
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L31/00
CPC分类号： H01L27/108 , G11C16/0408 , H01L27/10802 , H01L29/7841
摘要： A transistor fabrication method includes forming an electrode overlying a channel of a semiconductor on insulator (SOI) substrate. Source/drain structures are formed in the substrate on either side of the channel. The source/drain structures include a layer of a second semiconductor over a first semiconductor. The first and second semiconductors have different bandgaps. The second semiconductor extends under the gate electrode. The source/drain structures may be formed by doping the source/drain regions and etching the doped regions selectively to form voids. A film of the second semiconductor is then grown epitaxially to fill the void. A film of the first semiconductor may be grown to line the void before growing the second semiconductor. Alternatively, the second semiconductor is a continuous layer that extends through the channel body. A capping layer of the first semiconductor may lie over the second semiconductor in this embodiment.

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