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51. 发明授权

US06678200B2 Systems and methods for communicating with memory blocks 有权
标题翻译：与内存块通信的系统和方法
公开(公告)号：US06678200B2
公开(公告)日：2004-01-13
申请号：US10145834
申请日：2002-05-14
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C702
CPC分类号： G11C11/16
摘要： Systems and methods for reading from or writing to memory blocks, are provided. An embodiment of the system comprises a plurality of memory blocks; a plurality of repeaters; and a line that couples the memory blocks with the repeaters such that the repeaters can read from the memory blocks. One embodiment of the method comprises coupling the memory blocks to repeaters; and reading from the memory blocks.
摘要翻译：提供了从存储块读取或写入存储块的系统和方法。系统的实施例包括多个存储块; 多个中继器; 以及将存储器块与中继器耦合的线，使得中继器可以从存储器块读取。该方法的一个实施例包括将存储块耦合到转发器; 并从内存块读取。

52. 发明授权

US06636436B2 Isolation of memory cells in cross point arrays 失效
公开(公告)号：US06636436B2
公开(公告)日：2003-10-21
申请号：US09983701
申请日：2001-10-25
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C1100
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/16 , H01L27/228
摘要： A memory array includes memory cells located at cross points of first and second conductors. The memory cells are compound structures including an isolation element for isolating a memory cell from sneak path currents, and a re-writeable storage element for storing a binary state of the memory cell. The isolation elements include tunnel gate surface effect transistor gate oxides, and pillar diode structures. A control gate of the transistor disconnects the tunnel junction from sidewalls of the pillar, preventing sneak path current flow through the memory cells. The isolation elements in the memory cells do not require additional space on the substrate, allowing for a high array density. In addition, the memory cells have a low forward voltage drop, improving the readability of the memory array.

53. 发明授权

US06590804B1 Adjustable current mode differential amplifier 有权
标题翻译：可调电流模式差分放大器
公开(公告)号：US06590804B1
公开(公告)日：2003-07-08
申请号：US10198278
申请日：2002-07-16
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C1100
CPC分类号： G11C7/062 , G11C11/16 , G11C2207/063
摘要： An adjustable current mode differential sense amplifier is provided. The amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier. When a second bias voltage is applied to the memory and reference cells in order to determine the memory cell value, the amplifier is able to sense slight changes in the currents or voltages associated with the selected memory cell and the reference cell and compare them to determine the state of the memory cell. This increased sensitivity enables the amplifier to have a substantially increased dynamic range without introducing components that might adversely affect the memory circuitry parameters.
摘要翻译：提供可调电流模式差分读出放大器。放大器设置成与选定的存储单元和具有预定值的参考单元通信。放大器能够检测与所选存储单元相关联的电流和电压变化，并将其与参考单元相关的电流和电压变化进行比较。可以通过修改与施加到放大器中的选定晶体管的背栅极偏置相关的阈值电压来改变感测放大器的工作点。当将第一偏置电压施加到所选择的存储器单元以便最大化放大器的灵敏度时，该调整能力使得读出放大器的电流或电压被设置。当第二偏置电压施加到存储器和参考单元以便确定存储单元值时，放大器能够感测与所选择的存储器单元和参考单元相关联的电流或电压的轻微变化，并将其进行比较以确定存储单元的状态。这种增加的灵敏度使得放大器具有显着增加的动态范围，而不引入可能不利地影响存储器电路参数的组件。

54. 发明授权

US06584589B1 Self-testing of magneto-resistive memory arrays 有权
标题翻译：磁阻存储器阵列的自检
公开(公告)号：US06584589B1
公开(公告)日：2003-06-24
申请号：US09498588
申请日：2000-02-04
申请人： Frederick A. Perner , Kenneth J. Eldredge , Lung Tran
发明人： Frederick A. Perner , Kenneth J. Eldredge , Lung Tran
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C27/02 , G11C29/02 , G11C29/44
摘要： A collection of testing circuits are disclosed which can be used to form a comprehensive built-in test system for MRAM arrays. The combination of testing circuits can detect MRAM array defects including: open rows, shorted memory cells, memory cells which are outside of resistance specifications, and simple read/write pattern errors. The built-in test circuits include a wired-OR circuit connecting all the rows to test for open rows and shorted memory cells. A dynamic sense circuit detects whether the resistance of memory cells is within specified limits. An exclusive-OR gate combined with global write controls is integrated into the sense amplifiers and is used to perform simple read-write pattern tests. Error data from the margin tests and the read-write tests are reported through a second wired-OR circuit. Outputs from the two wired-OR circuits and the associated row addresses are reported to the test processor or recorded into an on-chip error status table.
摘要翻译：公开了一系列测试电路，可用于形成用于MRAM阵列的综合内置测试系统。测试电路的组合可以检测MRAM阵列缺陷，包括：开放行，短路存储单元，超出电阻规格的存储单元，以及简单的读/写模式错误。内置的测试电路包括连接所有行的线OR电路，以测试打开的行和短路存储单元。动态感测电路检测存储器单元的电阻是否在规定的范围内。与全局写入控制相结合的异或门被集成到读出放大器中，用于执行简单的读写模式测试。来自裕度测试和读写测试的错误数据通过第二个有线电路报告。来自两个有线OR电路和相关行地址的输出被报告给测试处理器或记录在片上错误状态表中。

55. 发明授权

US06456525B1 Short-tolerant resistive cross point array 有权
标题翻译：短路电阻交叉点阵列
公开(公告)号：US06456525B1
公开(公告)日：2002-09-24
申请号：US09663752
申请日：2000-09-15
申请人： Frederick A. Perner , Thomas C. Anthony
发明人： Frederick A. Perner , Thomas C. Anthony
IPC分类号： G11C1114
CPC分类号： H01L27/222 , G11C11/16 , G11C13/0004
摘要： A data storage device includes a resistive cross point array of memory cells. Each memory cell includes a memory element and a resistive element connected in series with the memory element. The resistive elements substantially attenuate any sneak path currents flowing through shorted memory elements during read operations. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.
摘要翻译：数据存储装置包括存储单元的电阻交叉点阵列。每个存储单元包括与存储元件串联连接的存储元件和电阻元件。电阻元件在读取操作期间基本上衰减流过短路存储器元件的任何潜行路径电流。数据存储装置可以是磁随机存取存储器（“MRAM”）装置。

56. 发明授权

US06324093B1 Write-once thin-film memory 有权
标题翻译：一次写薄膜记忆
公开(公告)号：US06324093B1
公开(公告)日：2001-11-27
申请号：US09663016
申请日：2000-09-15
申请人： Frederick A. Perner , Thomas C. Anthony
发明人： Frederick A. Perner , Thomas C. Anthony
IPC分类号： G11C1114
CPC分类号： G11C17/146 , G11C11/14
摘要： A data storage device includes a group of memory cells. Write-once operations may be performed by damaging the thin-film barriers of at least some of the memory cells. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.
摘要翻译：数据存储装置包括一组存储单元。可以通过损坏至少一些存储器单元的薄膜屏障来执行一次写入操作。数据存储装置可以是磁随机存取存储器（“MRAM”）装置。

57. 发明授权

US06227644B1 Inkjet dot imaging sensor for the calibration of inkjet print heads 失效
标题翻译：喷墨点式成像传感器用于校准喷墨打印头
公开(公告)号：US06227644B1
公开(公告)日：2001-05-08
申请号：US09072408
申请日：1998-05-04
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： B41J29393
CPC分类号： B41J2/2139 , B41J29/393
摘要： A print head for use in inkjet printers and the like. The print head includes a plurality of nozzles for delivering droplets of ink onto a print medium and thereby producing dots on the print medium. The print head also includes an imaging sensor for forming an image of the dots in response to a control signal. A controller in the print head reads out the image information to a processor connected to the print head. In one embodiment of the invention, the image is formed and readout in response to the detection of a dot from one of the nozzles by a sensor. In the preferred embodiment of the present invention, the nozzles are arranged in a regular array characterized by inter-nozzle spacing and the imaging sensor includes a rectangular two-dimensional array of photodetectors in which the photodetectors are spaced apart from one another by a distance less than the inter-nozzle spacing. Embodiments utilizing bit serial processors for processing the output of the detectors in each row of the two-dimensional array are also described.
摘要翻译：用于喷墨打印机等的打印头。打印头包括多个喷嘴，用于将墨滴输送到打印介质上，从而在打印介质上产生点。打印头还包括用于响应于控制信号形成点的图像的成像传感器。打印头中的控制器将图像信息读取到连接到打印头的处理器。在本发明的一个实施例中，响应于通过传感器从一个喷嘴检测到点而形成图像并读出图像。在本发明的优选实施例中，喷嘴布置成以喷嘴间间隔为特征的规则阵列，并且成像传感器包括光电检测器的矩形二维阵列，其中光电检测器彼此间隔距离较小比喷嘴间间距。还描述了利用位串行处理器来处理二维阵列的每行中的检测器的输出的实施例。

58. 发明授权

US6051867A Interlayer dielectric for passivation of an elevated integrated circuit sensor structure 有权
标题翻译：用于钝化升高的集成电路传感器结构的层间电介质
公开(公告)号：US6051867A
公开(公告)日：2000-04-18
申请号：US306238
申请日：1999-05-06
申请人： Jeremy A. Theil , Gary W. Ray , Frederick A. Perner , Min Cao
发明人： Jeremy A. Theil , Gary W. Ray , Frederick A. Perner , Min Cao
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L27/146 , H01L31/02 , H01L33/00
CPC分类号： H01L27/14601 , H01L31/02005
摘要： An integrated circuit sensor structure. The integrated circuit sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A dielectric layer is adjacent to the interconnect structure. The dielectric layer includes a planar surface, and conductive dielectric vias which pass through the dielectric layer and are electrically connected to the interconnect vias. The dielectric layer further includes an interlayer planarization dielectric layer adjacent to the interconnect structure, and a passivating layer adjacent to the interlayer planarization dielectric layer. The integrated circuit sensor structure further includes sensors adjacent to the dielectric layer. The interconnect vias and the dielectric vias electrically connect the electronic circuitry to the sensors.
摘要翻译：集成电路传感器结构。集成电路传感器结构包括包括电子电路的基板。互连结构与衬底相邻。互连结构包括通过互连结构的导电互连通孔。电介质层与互连结构相邻。电介质层包括平坦表面和穿过电介质层并电连接到互连通孔的导电电介质通孔。电介质层还包括与互连结构相邻的层间平坦化介电层和与层间平坦化介电层相邻的钝化层。集成电路传感器结构还包括与电介质层相邻的传感器。互连通孔和电介质通孔将电子电路电连接到传感器。

59. 发明申请

US20140359209A1 WORD SHIFT STATIC RANDOM ACCESS MEMORY (WS-SRAM) 有权
标题翻译： WORD移动静态随机存取存储器（WS-SRAM）
公开(公告)号：US20140359209A1
公开(公告)日：2014-12-04
申请号：US14374776
申请日：2012-01-30
申请人： Frederick A. Perner , Matthew D. Pickett
发明人： Frederick A. Perner , Matthew D. Pickett
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C11/407 , G11C11/412 , G11C19/28
摘要： Word shift static random access memory (WS-SRAM) cell, word shift static random access memory (WS-SRAM) and method using the same employ dynamic storage mode switching to shift data. The WS-SRAM cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data, a dynamic/static (D/S) mode selector to selectably switch the WS-SRAM cell between the dynamic storage mode and a static storage mode, and a column selector to selectably determine whether or not the WS-SRAM cell accepts shifted data. The WS-SRAM includes a plurality of WS-SRAM cells arranged in an array and a controller to shift data. The method includes switching a storage mode and activating a column selector of, coupling data from an adjacent memory cell to, and storing the coupled data in, a selected WS-SRAM cell.
摘要翻译：字移位静态随机存取存储器（WS-SRAM）单元，字移动静态随机存取存储器（WS-SRAM）和使用该方法的方法采用动态存储模式切换来移位数据。 WS-SRAM单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元，动态/静态（D / S）模式选择器，用于可选择地在动态存储器之间切换WS-SRAM单元模式和静态存储模式，以及列选择器，可选地确定WS-SRAM单元是否接受移位数据。 WS-SRAM包括排列成阵列的多个WS-SRAM单元和用于移位数据的控制器。该方法包括切换存储模式并激活列表选择器，将数据从相邻的存储器单元耦合到并将所耦合的数据存储在所选择的WS-SRAM单元中。

60. 发明授权

US07446683B2 Digital current source 有权
标题翻译：数字电流源
公开(公告)号：US07446683B2
公开(公告)日：2008-11-04
申请号：US11267705
申请日：2005-11-03
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： H03M1/00
CPC分类号： G05F3/262
摘要： A digital current source used to mirror a reference current is provided. The digitally controlled analog current source multiplies a current from a master mirror transistor producing an output current that is a digitally controlled multiple of the reference current. The circuit comprises a plurality of one bit current mirror cells. Each one bit current mirror cell comprises a mirror transistor receiving an analog gate voltage from a master mirror transistor and providing a drain voltage, an operational amplifier configured to maintain the drain voltage for the mirror transistor equivalent to the analog gate voltage, and a switch configured to receive one control bit, the switch enabling current mirroring when the mirror voltage is substantially equivalent to the master mirror voltage. The digital current source further includes a common line summing element employed to receive and compile currents from each of the one bit current mirror cells.
摘要翻译：提供了用于镜像参考电流的数字电流源。数字控制的模拟电流源将来自主镜晶体管的电流相乘，产生作为参考电流的数字控制倍数的输出电流。电路包括多个一位电流镜单元。每一位电流镜单元包括反射镜晶体管，其接收来自主镜晶体管的模拟栅极电压并提供漏极电压;运算放大器，被配置为保持反射镜晶体管的漏极电压等于模拟栅极电压;以及开关配置为了接收一个控制位，当镜电压基本上等于主镜电压时，该开关启用电流镜像。数字电流源还包括用于从一个位电流镜单元中的每一个接收和编译电流的公共线求和元件。

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