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51. 发明授权

US6111425A Very low power logic circuit family with enhanced noise immunity 有权
标题翻译：超低功耗逻辑电路系列，具有增强的抗噪声能力
公开(公告)号：US6111425A
公开(公告)日：2000-08-29
申请号：US173436
申请日：1998-10-15
申请人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Russell J. Houghton , Wilbur D. Pricer , William R. Tonti
IPC分类号： H03K19/003 , H03K3/356 , H03K19/173 , H03K17/16
CPC分类号： H03K3/356113 , H03K19/1738
摘要： A very low power logic circuit family which advantageously provides 1) retained high performance, 2) significantly reduced power dissipation, and 3) enhanced noise immunity. In a first set of embodiments, dual rail complementary logic signals are utilized to improve circuit immunity to external noise and to reduce noise generated by the logic circuit itself. A receiver portion of the present invention comprises two input FETs having cross coupling of the two gates to the two sources. In one preferred embodiment, both receiver and driver portions are connected in a repeater with all N channel drivers. A second set of embodiments have a single sided input in an unbalanced receiver comprising cross coupled source to gate N channel and cross coupled drain to gate P channel output transistors.
摘要翻译：一个非常低功率的逻辑电路系列，有利地提供1）保持高性能，2）显着降低的功耗，和3）增强的抗噪声能力。在第一组实施例中，使用双轨互补逻辑信号来提高对外部噪声的电路抗扰性并且减少由逻辑电路本身产生的噪声。本发明的接收机部分包括具有两个门到两个源的交叉耦合的两个输入FET。在一个优选实施例中，接收器和驱动器部分都连接在具有所有N个通道驱动器的中继器中。第二组实施例在不平衡接收机中具有单侧输入，包括到栅极N沟道的交叉耦合源极和栅极P沟道输出晶体管的交叉耦合漏极。

52. 发明授权

US6070262A Reconfigurable I/O DRAM 失效
标题翻译：可重配置I / O DRAM
公开(公告)号：US6070262A
公开(公告)日：2000-05-30
申请号：US833367
申请日：1997-04-04
申请人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
发明人： Mark W. Kellogg , Timothy J. Dell , Erik L. Hedberg , Claude L. Bertin
IPC分类号： G06F11/10 , G06F12/00 , G11C7/10 , G11C29/00
CPC分类号： G11C7/1057 , G06F11/1044 , G11C7/1006 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C7/1084
摘要： A Dynamic Random Access Memory (DRAM) configurable by eight (.times.8) or by nine (.times.9). The DRAM has nine Data Input/Outputs (I/Os). The memory array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is configured .times.8, one I/O is held in its high impedance state; one ninth of the DRAM's data path (between the array and the ninth I/O) is ignored; and, the entire array address space is available for data storage through eight I/Os. When the DRAM is configured .times.9, all nine I/Os are active; the DRAM I/O path is reconfigured with part of the array providing the ninth bit through the ninth I/O; and the array address space reduced by one-eighth. All nine bits may be from a common sub-array. Alternatively, sub-arrays may be paired so that when the DRAM is configured .times.9, eight bits are accessed in seven-eighths of one sub-array, with the ninth bit being accessed in one eighth of the other sub-array of the pair.
摘要翻译：动态随机存取存储器（DRAM）可由八（x8）或九（x9）配置。 DRAM具有9个数据输入/输出（I / O）。存储器阵列被分成两个或更多个子阵列，子阵列单元被布置成可寻址的行和列。当DRAM被配置为x8时，一个I / O保持在其高阻抗状态; DRAM的数据路径（阵列和第九个I / O之间）的九分之一被忽略; 并且整个阵列地址空间可用于通过八个I / O进行数据存储。当DRAM配置为x9时，所有9个I / O都有效; DRAM I / O路径被配置为通过第九个I / O提供第九位的阵列的一部分; 并且阵列地址空间减少了八分之一。所有9位可能来自公共子阵列。或者，子阵列可以配对，使得当DRAM被配置为x9时，在一个子阵列的七分之八中访问八个比特，其中第九比特在该对的另一个子阵列的八分之一中被访问。

53. 发明授权

US5502667A Integrated multichip memory module structure 失效
标题翻译：集成多芯片存储模块结构
公开(公告)号：US5502667A
公开(公告)日：1996-03-26
申请号：US120876
申请日：1993-09-13
申请人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard K. Kalter , Gordon A. Kelley, Jr.
发明人： Claude L. Bertin , Wayne J. Howell , Erik L. Hedberg , Howard K. Kalter , Gordon A. Kelley, Jr.
IPC分类号： H01L25/18 , G11C5/00 , H01L25/00 , H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , G11C5/02
CPC分类号： G11C5/06 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40618 , G11C5/04 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4911 , H01L2224/85207 , H01L2225/0651 , H01L2225/06517 , H01L2225/06551 , H01L2225/06572 , H01L2225/06582 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/19041 , H01L2924/19107
摘要： An integrated multichip memory module structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the appearance of a single, higher level memory chip. A memory subunit is formed having N memory chips with each memory chip of the subunit having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the module's I/O pins. A preformed electrical interface layer is employed at one end of the memory subunit to electrically interconnect the controlling logic chip with the memory chips comprising the subunit. The controlling logic chip has smaller dimensions than the dimensions of the memory chips comprising the subunit. A lead frame, having an inner opening extending therethrough, is secured to the electrical interface layer and the controlling logic chip is secured to the electrical interface layer so as to reside within the lead frame, thereby producing a dense multichip integrated circuit package. Corresponding fabrication techniques include an approach for facilitating metallization patterning on the side surface of the memory subunit.
摘要翻译：一种集成多芯片存储器模块结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得以更高级别的存储器芯片的外观定义更强大的存储器架构。形成具有N个存储器芯片的存储器子单元，该子单元的每个存储器芯片具有M个存储器件。控制逻辑芯片协调与N个存储器芯片的外部通信，使得在模块的I / O引脚上出现具有NxM存储器件的单个存储器芯片架构。在存储器子单元的一端采用预先形成的电接口层，以将控制逻辑芯片与包括该子单元的存储器芯片电互连。控制逻辑芯片的尺寸小于包含子单元的存储器芯片的尺寸。具有延伸穿过其中的内部开口的引线框固定到电接口层，并且控制逻辑芯片固定到电接口层以便驻留在引线框架内，从而产生致密的多芯片集成电路封装。相应的制造技术包括促进存储器子单元的侧表面上的金属化图案化的方法。

54. 发明授权

US4602170A Resistive gate field effect transistor logic family 失效
标题翻译：电阻栅场效应晶体管逻辑系列
公开(公告)号：US4602170A
公开(公告)日：1986-07-22
申请号：US530450
申请日：1983-09-08
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/43 , H01L29/78 , H03K19/0944 , H03K19/094 , H03K19/20
CPC分类号： H01L29/435 , H03K19/09441
摘要： A family of digital logic circuits constructed with resistive gate field effect transistors is provided. The logic circuits are comprised of AND and OR circuits, each implemented with resistive gate devices. In constructing the AND circuit, the resistive gate lies along the length of the channel region between the source and drain of the device. Logic input signals are selectively applied along the length of the channel region to the resistive gate. The device will conduct between source and drain only if all points along the channel are above the local threshold voltage of the channel region which will occur when appropriate logic signals are applied simultaneously to all logic input terminals. A logic OR device is realized when the resistive gate is formed transverse to the channel such that each input to the gate controls a portion of the channel between the source and drain. NAND and NOR circuits are provided using the resistive gate logic device in an inverter circuit.
摘要翻译：提供了由电阻栅场效应晶体管构成的数字逻辑电路系列。逻辑电路由AND和OR电路组成，每个电路都使用电阻栅极器件实现。在构建AND电路时，电阻栅极沿着器件的源极和漏极之间的沟道区域的长度。选择性地将逻辑输入信号沿通道区域的长度施加到电阻门。只有沿着通道的所有点都高于通道区域的局部阈值电压，器件才会在源极和漏极之间导通，当适当的逻辑信号同时施加到所有逻辑输入端子时，该通道区域将发生。当电阻栅极横穿于通道形成时，实现逻辑或器件，使得到栅极的每个输入控制源极和漏极之间的沟道的一部分。在逆变器电路中使用电阻门逻辑器件提供NAND和NOR电路。

55. 发明授权

US4139935A Over voltage protective device and circuits for insulated gate transistors 失效
标题翻译：绝缘栅极晶体管的过电压保护器件和电路
公开(公告)号：US4139935A
公开(公告)日：1979-02-20
申请号：US782574
申请日：1977-03-29
申请人： Claude L. Bertin , Francisco H. De La Moneda
发明人： Claude L. Bertin , Francisco H. De La Moneda
IPC分类号： H03F1/52 , H01L21/265 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/06 , H01L29/06 , H01L29/78 , H02H7/20 , H03F1/42 , H03K17/0812 , H01L21/26
CPC分类号： H01L27/0251 , H01L21/2652 , H01L29/0688 , H03K17/08122
摘要： Protective devices and circuits for insulated gate transistors are improved by another p/n junction diode or MOS diode preventing breakdown of the thin oxide of the protective device. The breakdown voltage of the protective device or p/n diode may be tailored to a preselected voltage by altering its metallurgical junction by ion implantation or other techniques. Tailoring permits the breakdown voltage of the protective device to be independent of process and circuit specification of a protected or internal circuit. A plurality of parallel circuits connected as a protective device limits or controls secondary breakdown of the protective device.
摘要翻译：用于绝缘栅极晶体管的保护器件和电路由另一个p / n结二极管或MOS二极管改善，以防止保护器件的薄氧化物破坏。保护装置或p / n二极管的击穿电压可以通过改变其冶金接合通过离子注入或其它技术来调整为预选电压。裁缝允许保护装置的击穿电压与受保护或内部电路的工艺和电路规格无关。作为保护装置连接的多个并联电路限制或控制保护装置的二次击穿。

56. 发明授权

US09911743B2 Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same 有权
公开(公告)号：US09911743B2
公开(公告)日：2018-03-06
申请号：US11835852
申请日：2007-08-08
申请人： Claude L. Bertin , Thomas Rueckes , X. M. Henry Huang , Ramesh Sivarajan , Eliodor G. Ghenciu , Steven L. Konsek , Mitchell Meinhold , Jonathan W. Ward , Darren K. Brock
发明人： Claude L. Bertin , Thomas Rueckes , X. M. Henry Huang , Ramesh Sivarajan , Eliodor G. Ghenciu , Steven L. Konsek , Mitchell Meinhold , Jonathan W. Ward , Darren K. Brock
IPC分类号： H01L27/102 , B82Y10/00 , G11C13/02 , H01L21/822 , H01L27/06 , H01L27/12
CPC分类号： H01L27/1021 , B82Y10/00 , G11C13/025 , G11C2213/19 , G11C2213/71 , G11C2213/72 , H01L21/8221 , H01L27/0688 , H01L27/1203
摘要： Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals. In some embodiments, the first and second conductive terminals and the multilayer nanotube fabric are lithographically patterned so as to each have substantially the same lateral dimensions, e.g., to each have a substantially circular or rectangular lateral shape. In some embodiments, the multilayer nanotube fabric has a thickness from 10 nm to 200 nm, e.g., 10 nm to 50 nm. The structure may include an addressable diode provided under the first conductive terminal or deposited over the second terminal.

57. 发明授权

US09196615B2 Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same 有权
标题翻译：非挥发性纳米管二极管和非易失性纳米管块及使用其的系统及其制造方法
公开(公告)号：US09196615B2
公开(公告)日：2015-11-24
申请号：US11835865
申请日：2007-08-08
申请人： Claude L. Bertin , Thomas Rueckes , X. M. Henry Huang , Ramesh Sivarajan , Eliodor G. Ghenciu , Steven L. Konsek , Mitchell Meinhold
发明人： Claude L. Bertin , Thomas Rueckes , X. M. Henry Huang , Ramesh Sivarajan , Eliodor G. Ghenciu , Steven L. Konsek , Mitchell Meinhold
IPC分类号： G11C11/36 , H01L27/102 , B82Y10/00 , G11C13/02 , H01L21/822 , H01L23/525 , H01L27/06 , H01L27/12
CPC分类号： H01L27/1021 , B82Y10/00 , G11C13/025 , G11C2213/19 , H01L21/8221 , H01L23/5256 , H01L27/0688 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： Under one aspect, a nanotube diode includes: a cathode formed of a semiconductor material; and an anode formed of nanotubes. The cathode and anode are in fixed and direct physical contact, and are constructed and arranged such that sufficient electrical stimulus applied to the cathode and the anode creates a conductive pathway between the cathode and the anode. In some embodiments, the anode includes a non-woven nanotube fabric having a plurality of unaligned nanotubes. The non-woven nanotube fabric may have a thickness, e.g., of 0.5 to 20 nm. Or, the non-woven nanotube fabric may include a block of nanotubes. The nanotubes may include metallic nanotubes and semiconducting nanotubes, and the cathode may include an n-type semiconductor material. A Schottky barrier can form between the n-type semiconductor material and the metallic nanotubes and/or a PN junction can form between the n-type semiconductor material and the semiconducting nanotubes.
摘要翻译：在一个方面，纳米管二极管包括：由半导体材料形成的阴极; 和由纳米管形成的阳极。阴极和阳极是固定和直接的物理接触，并被构造和布置成使得施加到阴极和阳极的足够的电刺激在阴极和阳极之间产生导电通路。在一些实施方案中，阳极包括具有多个未对准纳米管的无纺布纳米管织物。无纺布纳米管织物可以具有例如0.5至20nm的厚度。或者，无纺布纳米管织物可以包括纳米管块。纳米管可以包括金属纳米管和半导体纳米管，并且阴极可以包括n型半导体材料。可以在n型半导体材料和金属纳米管之间形成肖特基势垒，和/或在n型半导体材料和半导体纳米管之间形成PN结。

58. 发明授权

US08809917B2 Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks 有权
标题翻译：存储元件和交叉点开关以及使用非易失性纳米管块的阵列
公开(公告)号：US08809917B2
公开(公告)日：2014-08-19
申请号：US12511779
申请日：2009-07-29
申请人： Claude L. Bertin , X. M. Henry Huang , Thomas Rueckes , Ramesh Sivarajan
发明人： Claude L. Bertin , X. M. Henry Huang , Thomas Rueckes , Ramesh Sivarajan
IPC分类号： H01L29/84
CPC分类号： G11C5/063 , B82Y10/00 , G11C13/0002 , G11C13/0021 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2213/19 , G11C2213/77 , G11C2213/79 , H01L27/10 , H01L27/105 , H01L27/1052 , H01L27/112 , H01L29/0665 , H01L29/0669 , H01L29/0673 , H01L51/0048 , H01L51/0591 , Y10S977/943
摘要： Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals. For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.
摘要翻译：在一个方面，覆盖的纳米管开关包括：（a）包括不对齐的多个纳米管的纳米管元件，所述纳米管元件具有顶表面，底表面和侧表面; （b）与纳米管元件接触的第一和第二端子，其中第一端子设置在并基本上覆盖纳米管元件的整个顶表面，并且其中第二端子接触纳米管的底表面的至少一部分元件; 和（c）能够向第一和第二端子施加电刺激的控制电路。纳米管元件可以响应于由控制电路施加到第一和第二端子的对应的多个电刺激而在多个电子状态之间切换。对于每个不同的电子状态，纳米管元件提供在第一和第二端子之间具有不同电阻的电路径。

59. 发明授权

US08471238B2 Light emitters using nanotubes and methods of making same 有权
标题翻译：使用纳米管的发光体及其制作方法
公开(公告)号：US08471238B2
公开(公告)日：2013-06-25
申请号：US11227468
申请日：2005-09-15
申请人： Jonathan W. Ward , Mitchell Meinhold , Claude L. Bertin , Benjamin Schlatka , Brent M. Segal , Thomas Ruckes
发明人： Jonathan W. Ward , Mitchell Meinhold , Claude L. Bertin , Benjamin Schlatka , Brent M. Segal , Thomas Ruckes
IPC分类号： H01L29/06
CPC分类号： H01K1/04 , B82Y10/00 , B82Y20/00 , H01L51/0048 , H01L51/0052
摘要： Light emitters using nanotubes and methods of making same. A light emitter includes a nanotube article in electrical communication with a first and a second contact, a substrate having a predefined region with a relatively low thermal conductivity said region in predefined physical relation to said nanotube article; and a stimulus circuit in electrical communication with the first and second contacts. The stimulus circuit provides electrical stimulation sufficient to induce light emission from the nanotube article in the proximity of the predefined region. The predefined region is a channel formed in the substrate or a region of material with relatively low thermal conductivity. The light emitter can be integrated with semiconductor circuits including CMOS circuits. The light emitter can be integrated into optical driver circuits (on- and off-chip drivers) and opto-isolators.
摘要翻译：使用纳米管的发光体及其制作方法。光发射器包括与第一和第二接触电连通的纳米管制品，具有预定区域的基底，所述预定区域具有相对于所述纳米管制品预定的物理关系的相对低导热性的所述区域; 以及与第一和第二触点电连通的激励电路。刺激电路提供足以在预定区域附近从纳米管制品引发光发射的电刺激。预定区域是形成在衬底中的通道或具有相对较低热导率的材料区域。光发射器可以与包括CMOS电路的半导体电路集成。光发射器可以集成到光驱动器电路（片上和片外驱动器）和光隔离器中。

60. 发明授权

US07985906B2 Nanotube-based switching elements and logic circuits 有权
标题翻译：基于纳米管的开关元件和逻辑电路
公开(公告)号：US07985906B2
公开(公告)日：2011-07-26
申请号：US12951896
申请日：2010-11-22
申请人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
发明人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
IPC分类号： H03K19/20 , H01L29/84
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/16 , G11C2213/17 , H01H1/0094 , H01H1/027 , H01H2001/0005 , H01L27/28 , H01L29/0673 , H01L29/73 , H01L29/78 , H01L51/0048 , H01L51/0508 , Y10S977/762 , Y10S977/932 , Y10S977/94 , Y10T29/49002
摘要： Nanotube-based switching elements and logic circuits are disclosed. Under one embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.
摘要翻译：公开了基于纳米管的开关元件和逻辑电路。在本发明的一个实施例中，布尔逻辑电路包括至少一个输入端子和输出端子，以及电气设置在所述至少一个输入端子和所述输出端子之间的纳米管开关元件网络。纳米管切换元件的网络在所述至少一个输入端上实现布尔信号的布尔函数变换。布尔函数变换包括函数内的布尔反转，如NOT或NOR函数。

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