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51. 发明授权

US5118382A Elimination of etch stop undercut 失效
标题翻译：消除冲击停止
公开(公告)号：US5118382A
公开(公告)日：1992-06-02
申请号：US565574
申请日：1990-08-10
申请人： John E. Cronin , Mark N. Lakritz
发明人： John E. Cronin , Mark N. Lakritz
IPC分类号： H01L21/306 , H01L21/311 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/31144
摘要： Two methods for wet etch removing an etch stop layer without leaving an undesired undercut are disclosed. In the first method, a reactive ion etch is stopped on an etch stop layer. The exposed etch stop is wet etch removed, leaving an undesirable undercut. The undercut is filled by chemical vapor deposition of a fill material. The filler is then etched to leave a smooth aperture without undercuts. This last etch may be a sputter etch followed by a plasma etch. In the second method, a reactive ion etch is stopped on an etch stop layer as in the first method. Sacrificial sidewalls are then formed within the aperture. The exposed etch stop layer is then removed by wet etching, the positioning of the sidewalls serving to prevent undercutting of the etch stop layer. Finally, the sacrificial sidewalls are etched.
摘要翻译：公开了用于湿蚀刻去除蚀刻停止层而不留下不期望的底切的两种方法。在第一种方法中，在蚀刻停止层上停止反应离子蚀刻。暴露的蚀刻停止是湿蚀刻去除，留下不希望的底切。底切被填充材料的化学气相沉积填充。然后对填料进行蚀刻以留下没有底切的光滑孔。该最后的蚀刻可以是溅射蚀刻，随后是等离子体蚀刻。在第二种方法中，如在第一种方法中一样，在蚀刻停止层上停止反应离子蚀刻。然后在孔内形成牺牲侧壁。然后通过湿蚀刻去除暴露的蚀刻停止层，侧壁的定位用于防止蚀刻停止层的底切。最后，蚀刻牺牲侧壁。

52. 发明授权

US4789648A Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias 失效
标题翻译：在基板上制造共面多层金属/绝缘体膜并与螺柱通孔同时形成图案化导电线的方法
公开(公告)号：US4789648A
公开(公告)日：1988-12-06
申请号：US791887
申请日：1985-10-28
申请人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
发明人： Melanie M. Chow , John E. Cronin , William L. Guthrie , Carter W. Kaanta , Barbara Luther , William J. Patrick , Kathleen A. Perry , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/302 , H01L21/304 , H01L21/3065 , H01L21/3213 , H01L21/768 , H05K3/04 , H05K3/10 , H05K3/46 , H01L21/306
CPC分类号： H01L21/7681 , H01L21/304 , H01L21/32134 , H01L21/7684 , H01L21/76877 , H05K3/04 , H05K3/107 , H05K3/4644
摘要： Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time.Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material.The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.
摘要翻译：图案化的导线通过连接通过绝缘层与螺柱同时形成，以预先形成的多层VLSI芯片技术中的下面的图案化导电线。第一平坦化绝缘层沉积在要选择性地建立触点的图案化导电材料的第一层上。第一层然后被蚀刻停止材料覆盖。在需要螺柱连接器的位置处，在蚀刻停止材料中限定接触孔。此时第一层绝缘层不被蚀刻。接下来，将第二平坦化绝缘层沉积在蚀刻停止材料上。再次通过光刻将第二层绝缘层蚀刻到蚀刻停止材料上，以限定所需的布线通道，其中的一些布线通道将与蚀刻停止材料中先前形成的接触孔对准。在暴露接触孔的那些位置中，蚀刻继续进入第一绝缘层，以露出图案化的导电材料的下面的第一层。通道和通孔充满金属化。通过蚀刻或化学机械（chemical-mechanical）抛光去除多余的金属化。

53. 发明授权

US07787169B2 Electro-optic displays, and methods for driving same 有权
标题翻译：电光显示器及其驱动方法
公开(公告)号：US07787169B2
公开(公告)日：2010-08-31
申请号：US10907171
申请日：2005-03-23
申请人： Justin J. Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler , Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Ian D. Morrison , Steven J. O'Neil , Richard J. Paolini, Jr. , Anthony Edward Pullen , Jianna Wang , Jonathan L. Zalesky , Robert W. Zehner , John E. Cronin
发明人： Justin J. Abramson , Karl R. Amundson , Guy M. Danner , Gregg M. Duthaler , Holly G. Gates , Charles H. Honeyman , Ara N. Knaian , Ian D. Morrison , Steven J. O'Neil , Richard J. Paolini, Jr. , Anthony Edward Pullen , Jianna Wang , Jonathan L. Zalesky , Robert W. Zehner , John E. Cronin
IPC分类号： G02F1/153
CPC分类号： G02F1/15 , G02F1/1521 , G02F2201/42
摘要： The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters.
摘要翻译：本发明涉及用于驱动这种显示器的电光显示器和方法。本发明提供（i）具有固体电荷传输层的电致变色显示器; （ii）用于改善电色差显示器的对比度和降低成本的装置和方法; （iii）从外部环境密封电致变色显示器并防止污染物进入这种显示器的装置和方法; 和（iv）用于调节电光显示器的驱动以允许环境和操作参数的方法。

54. 发明授权

US06590290B1 Stacked via in copper/polyimide BEOL 有权
标题翻译：通过铜/聚酰亚胺BEOL堆叠
公开(公告)号：US06590290B1
公开(公告)日：2003-07-08
申请号：US09532229
申请日：2000-03-22
申请人： John E. Cronin , Barbara J. Luther
发明人： John E. Cronin , Barbara J. Luther
IPC分类号： H01L2348
CPC分类号： H01L21/7681 , H01L21/76805 , H01L21/76813 , H01L21/7684 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.
摘要翻译：一种结构和方法，用于通过形成要在其上形成接触的第一互连区域，在所述互连区域上方形成第一绝缘层，以及在所述互连区域上方的蚀刻停止层第一绝缘层，并蚀刻蚀刻停止层，以在第一互连区域上方的位置形成开口。第二互连区形成为与第一绝缘层接触并且在第一互连区上方形成，第二绝缘层形成在第一绝缘层和蚀刻停止层之上，并且在第二绝缘层中形成与开口重叠的开口在蚀刻停止层中。第二绝缘层中的开口延伸穿过第一绝缘层，并且第一和第二绝缘层中的开口填充有导体，以在第一互连区域和第二绝缘层上方的区域之间形成连接。

55. 发明授权

US06440858B1 Multi-layer hard mask for deep trench silicon etch 失效
标题翻译：用于深沟槽硅蚀刻的多层硬掩模
公开(公告)号：US06440858B1
公开(公告)日：2002-08-27
申请号：US09138964
申请日：1998-08-24
申请人： Anthony J. Canale , John E. Cronin
发明人： Anthony J. Canale , John E. Cronin
IPC分类号： H01L21302
CPC分类号： H01L21/3085 , H01L21/3065 , H01L21/3081 , H01L21/31111 , H01L27/1087
摘要： A method of etching multiple films with a dual layer hard mask wherein one layer is totally removed and the other layer partially removed during deep trench etching of the silicon substrate. In particular, a method of deep trench etching silicon substrates comprising the steps of providing a semiconductor substrate capable of being etched, with HBr/NF3/He/O2, having a layer of pad dielectric disposed depositing a layer of material capable of selective removability with respect to the pad dielectric, preferably BSG; depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric, preferably, silicon oxide deposited by PECVD; patterning at least one of the layers, and etching the semiconductor substrate to form a trench and removing the layer of material having a slower etch rate than the semiconductor substrate, wherein trenches are of close proximity to each other.
摘要翻译：一种用双层硬掩模蚀刻多个膜的方法，其中在硅衬底的深沟槽蚀刻期间完全去除一层，另一层部分去除。特别地，深沟槽蚀刻硅衬底的方法包括以下步骤：提供能够用HBr / NF 3 / He / O 2蚀刻的半导体衬底，该HBr / NF 3 / He / O 2具有一层衬垫电介质，其设置有沉积能够选择性移除的材料层，相对于焊盘电介质，优选BSG; 沉积具有比半导体衬底更慢的蚀刻速率的材料层和能够相对于焊盘电介质优选地通过PECVD沉积的氧化硅能够选择性移除的材料层; 图案化至少一个层，并且蚀刻半导体衬底以形成沟槽并去除具有比半导体衬底更低的蚀刻速率的材料层，其中沟槽彼此靠近。

56. 发明授权

US06229155B1 Semiconductor and method of fabricating 失效
标题翻译：半导体及其制造方法
公开(公告)号：US06229155B1
公开(公告)日：2001-05-08
申请号：US09087612
申请日：1998-05-29
申请人： Daniel S. Brooks , Phillip F. Chapman , John E. Cronin , Richard E. Wistrom
发明人： Daniel S. Brooks , Phillip F. Chapman , John E. Cronin , Richard E. Wistrom
IPC分类号： H01L2972
CPC分类号： H01L21/28017 , H01L21/28176 , H01L21/28194 , H01L21/28211 , H01L21/28247
摘要： Provided is a semiconductor structure that comprises a substrate; a conductor; and insulating layer separating the conductor from the substrate; and a removable conductive strap coupled to the conductor and the substrate for maintaining a common voltage between the conductor and substrate during ion beam and/or plasma processing; and a method for fabricating.
摘要翻译：提供一种包括基板的半导体结构; 指挥以及将导体与基板分离的绝缘层; 以及耦合到所述导体和所述衬底的可移除导电带，用于在离子束和/或等离子体处理期间在所述导体和衬底之间维持公共电压; 和制造方法。

57. 发明授权

US6143640A Method of fabricating a stacked via in copper/polyimide beol 失效
标题翻译：在铜/聚酰亚胺蜂窝中制造堆叠通孔的方法
公开(公告)号：US6143640A
公开(公告)日：2000-11-07
申请号：US936090
申请日：1997-09-23
申请人： John E. Cronin , Barbara J. Luther
发明人： John E. Cronin , Barbara J. Luther
IPC分类号： H05K3/46 , H01L21/306 , H01L21/768 , H01L23/12 , H01L23/522 , H01L23/538
CPC分类号： H01L21/7681 , H01L21/76805 , H01L21/76813 , H01L21/7684 , H01L23/5226 , H01L2924/0002
摘要： A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.
摘要翻译：一种结构和方法，用于通过形成要在其上形成接触的第一互连区域，在所述互连区域上方形成第一绝缘层，以及在所述互连区域上方的蚀刻停止层第一绝缘层，并蚀刻蚀刻停止层，以在第一互连区域上方的位置形成开口。第二互连区形成为与第一绝缘层接触并且在第一互连区上方形成，第二绝缘层形成在第一绝缘层和蚀刻停止层之上，并且在第二绝缘层中形成与开口重叠的开口在蚀刻停止层中。第二绝缘层中的开口延伸穿过第一绝缘层，并且第一和第二绝缘层中的开口填充有导体，以在第一互连区域和第二绝缘层上方的区域之间形成连接。

58. 发明授权

US5602051A Method of making stacked electrical device having regions of electrical isolation and electrical connection on a given stack level 失效
标题翻译：在给定的堆叠级上制造具有电隔离和电连接区域的堆叠电气装置的方法
公开(公告)号：US5602051A
公开(公告)日：1997-02-11
申请号：US540387
申请日：1995-10-06
申请人： John E. Cronin , John K. DeBrosse , Hing Wong
发明人： John E. Cronin , John K. DeBrosse , Hing Wong
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L2924/0002
摘要： An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.
摘要翻译：公开了一种用于隔离彼此定位的电导体的改进方法。这些导体通常彼此接触，因为用于制造多个导电元件（例如非常致密的半导体结构）的图案化和蚀刻步骤有些不精确。该方法包括在下导体的上表面中形成凹部，然后用氧化物型材料至少部分地填充凹部。该方法在叠层电容器单元的构造中特别有价值。使用该技术制备的细胞也构成本发明的一部分。

59. 发明授权

US5589707A Multi-surfaced capacitor for storing more charge per horizontal chip area 失效
标题翻译：多表面电容器用于每个水平芯片区域存储更多的电荷
公开(公告)号：US5589707A
公开(公告)日：1996-12-31
申请号：US335012
申请日：1994-11-07
申请人： John E. Cronin
发明人： John E. Cronin
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L29/94 , H01L27/108 , H01L29/00
CPC分类号： H01L28/82 , H01L29/94
摘要： An integrated circuit capacitor device that increases capacitance without proportionately using more substrate surface area. Uniquely, the capacitor uses up to all four sides of the first charge plate to store charge by surrounding it with a second charge plate with an insulator layer separating the two plates.
摘要翻译：一种集成电路电容器件，其增加电容而不成比例地使用更多的衬底表面积。独特地，电容器使用直到第一充电板的所有四个侧面以通过用第二充电板围绕它来存储电荷，其中绝缘体层分隔两个板。

60. 发明授权

US5556802A Method of making corrugated vertical stack capacitor (CVSTC) 失效
标题翻译：波纹垂直叠层电容器（CVSTC）制作方法
公开(公告)号：US5556802A
公开(公告)日：1996-09-17
申请号：US486630
申请日：1995-06-07
申请人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
发明人： Paul E. Bakeman, Jr. , Bomy A. Chen , John E. Cronin , Steven J. Holmes , Hing Wong
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/82 , H01L28/84 , H01L28/90 , Y10S438/949
摘要： A method for forming a capacitor on a substrate having a contact below a top layer including the steps of:Spinning on a layer of photoresist material. Exposing the photoresist to light to establish a standing wave pattern to fix prominences of photoresist separated by separation areas. Each prominence extends a prominence height from the top layer to a top. Developing the photoresist to fix an erose face on each prominence, each face extending from the top layer to the top. Depositing a first oxide intermediate prominences to effect accumulation of the first oxide to an oxide height at least equal to the prominence height. Etching the first oxide to expose each top. Dissolving the photoresist to uncover oxide mandrels. Each mandrel extends a mandrel height from the top layer to a mandrel top; each mandrel has an erose mandrel face intermediate the top layer and the mandrel top. Etching the top layer to expose the contact. Depositing a first silicon material over selected mandrels, the top layer, and the contact intermediate the selected mandrels. Depositing photoresist over the first silicon. Etching the photoresist and the first silicon to the mandrel height to establish a node capacitor electrode. Stripping the photoresist remaining. Stripping the first oxide. Depositing a second oxide over the node electrode to establish a capacitor dielectric layer. Depositing a second silicon material over the dielectric layer to establish a plate capacitor electrode.
摘要翻译：一种在具有在顶层之下具有接触的基底上形成电容器的方法，包括以下步骤：在光致抗蚀剂材料层上旋转。将光致抗蚀剂曝光以建立驻波图案以固定由分离区域分离的光致抗蚀剂的突出部分。每个突出部分从顶层延伸到顶部。显影光致抗蚀剂以在每个突起处固定一个正面，每个面从顶层延伸到顶部。沉积第一氧化物中间体以使第一氧化物积累至至少等于突出高度的氧化物高度。蚀刻第一氧化物以暴露每个顶部。溶解光致抗蚀剂以露出氧化物心轴。每个心轴将心轴高度从顶层延伸到心轴顶部; 每个心轴具有在顶层和心轴顶部之间的中心轴。蚀刻顶层以暴露接触。将第一硅材料沉积在选定的心轴，顶层和选定的心轴之间的接触之上。在第一硅上沉积光致抗蚀剂。将光致抗蚀剂和第一硅蚀刻到心轴高度以建立节点电容器电极。剥离残留的光致抗蚀剂。剥去第一氧化物。在节点电极上沉积第二氧化物以建立电容器介电层。在电介质层上沉积第二硅材料以建立平板电容器电极。

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