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51. 发明授权

US07818137B2 Characterization circuit for fast determination of device capacitance variation 失效
标题翻译：用于快速确定器件电容变化的表征电路
公开(公告)号：US07818137B2
公开(公告)日：2010-10-19
申请号：US12361891
申请日：2009-01-29
申请人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
发明人： Kanak B. Agarwal , Jerry D. Hayes , Sani R. Nassif
IPC分类号： G01R27/00 , G01R31/00 , G01R31/14
CPC分类号： G01R31/2884 , G01R31/2831 , G01R31/318533 , G01R31/318558
摘要： A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.
摘要翻译：用于快速确定器件电容变化统计的测试电路提供了一种使用低计算能力和易于获得的测试设备来确定过程变化和参数统计的机制。在计算机控制下刺激具有可单独选择的装置的测试阵列以依次选择每个装置。阵列的测试输出提供依赖于特定器件参数的电流或电压。器件的顺序选择产生电压或电流波形，其特性使用与计算机连接的数字万用表进行测量。测试输出端的电流或电压的有效值表示参数变化的标准偏差，电流或电压的直流值表示参数的平均值。

52. 发明申请

US20100225348A1 METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION 失效
标题翻译：用于统计CMOS器件特征的方法和装置
公开(公告)号：US20100225348A1
公开(公告)日：2010-09-09
申请号：US12779038
申请日：2010-05-12
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.
摘要翻译：使用具有大量被测电子器件的统一测试结构来表征器件的电容电压参数（C-V）和电流 - 电压参数（I-V）。这些器件被排列成列和行的阵列，并由控制逻辑选择，该逻辑门将不同地作为电流源，吸收器，钳位，测量端口和检测线的输入/输出引脚进行门控。通过对不同的激发电压频率进行基线和激励电流测量来测量电容电压参数，计算基线和激励电流测量之间的电流差异，并产生电流差与不同频率之间的线性关系。然后通过将表示线性关系的线的斜率除以激励电压来导出电容。可以对不同的电子设备进行测试，包括晶体管和互连结构。

53. 发明授权

US07782076B2 Method and apparatus for statistical CMOS device characterization 失效
公开(公告)号：US07782076B2
公开(公告)日：2010-08-24
申请号：US12141862
申请日：2008-06-18
申请人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
发明人： Kanak B. Agarwal , Jerry D. Hayes , Ying Liu
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/3181 , G01R31/3004
摘要： A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures.

54. 发明授权

US07759991B2 Scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics 失效
标题翻译：可扫描的虚拟轨道环形振荡器电路和用于测量器件特性变化的系统
公开(公告)号：US07759991B2
公开(公告)日：2010-07-20
申请号：US12356145
申请日：2009-01-20
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： H03F3/66 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/318577 , H03K3/0315 , H03K2005/00058 , H03K2005/00234
摘要： A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.
摘要翻译：用于测量器件特性变化的可扫描虚拟轨道环形振荡器电路和系统提供了使用环形振荡器频率测量来研究随机器件特性变化以及N沟道和P沟道器件之间的系统差异的能力。环形振荡器通过由可编程源控制的多个晶体管连接到实际电源轨的至少一个虚拟电源轨来操作。晶体管沿着环形振荡器元件的物理分布物理分布，并且可以依次启用晶体管，并测量环形振荡器频率的变化。可以通过使用具有相应P沟道和N沟道控制晶体管的正和负虚拟电源轨来研究环形振荡器频率测量产生关于晶体管与N沟道与P沟道变化之间变化的信息。

55. 发明授权

US07532078B2 Scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics 失效
标题翻译：可扫描虚拟轨道法和环形振荡器电路，用于测量器件特性的变化
公开(公告)号：US07532078B2
公开(公告)日：2009-05-12
申请号：US11673025
申请日：2007-02-09
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： H03F3/66 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/318577 , H03K3/0315 , H03K2005/00058 , H03K2005/00234
摘要： A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.
摘要翻译：用于测量器件特性变化的可扫描虚拟轨迹法和环形振荡器电路提供了研究随机器件特性变化以及使用环形振荡器频率测量的N沟道和P沟道器件之间的系统差异的能力。环形振荡器通过由可编程源控制的多个晶体管连接到实际电源轨的至少一个虚拟电源轨来操作。晶体管沿着环形振荡器元件的物理分布物理分布，并且可以依次启用晶体管，并测量环形振荡器频率的变化。可以通过使用具有相应P沟道和N沟道控制晶体管的正和负虚拟电源轨来研究环形振荡器频率测量产生关于晶体管与N沟道与P沟道变化之间变化的信息。

56. 发明申请

US20080255792A1 TEST SYSTEM AND COMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY 失效
标题翻译：使用设备阵列确定阈值电压变化的测试系统和计算机程序
公开(公告)号：US20080255792A1
公开(公告)日：2008-10-16
申请号：US12147290
申请日：2008-06-26
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G01R31/00
CPC分类号： G01R31/2884 , G01R31/2621 , G01R31/275
摘要： A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.
摘要翻译：用于使用器件阵列测量阈值电压变化的测试系统和计算机程序为过程验证和改进提供了准确的阈值电压分布值。测试系统和计算机程序控制表征阵列电路，其在阵列内的各个器件上施加固定的漏极 - 源极电压和恒定沟道电流。另一个电路感测阵列内各个器件的源极电压。阈值电压的统计分布直接由源电压分布确定，通过将每个源极电压抵消通过完全表征阵列内的一个或多个器件而确定的值。所得到的方法避免了对阵列内的每个器件进行表征的必要性，从而显着地减少了测量时间。

57. 发明授权

US09507250B2 Optical proximity correction for improved electrical characteristics 有权
标题翻译：光学接近校正，改善电气特性
公开(公告)号：US09507250B2
公开(公告)日：2016-11-29
申请号：US12640166
申请日：2009-12-17
申请人： Kanak B. Agarwal , Sani R. Nassif
发明人： Kanak B. Agarwal , Sani R. Nassif
IPC分类号： G06F17/50 , G03F1/00 , G03F1/36
CPC分类号： G03F1/144 , G03F1/36
摘要： A method, computer program product, and data processing system for performing an improved optical proximity correction are disclosed, which better respect the electrical properties of the device being manufactured. A preferred embodiment of the present invention performs OPC by first dividing the perimeter of a mask region into a plurality of segments, then grouping the segments into at least two distinct groups, wherein segments in the first of these groups are adjusted in position so as to minimize edge placement error (EPE) when the photolithography using the mask is simulated. Segments in the second group are adjusted in position so as to minimize cumulative error in a dimension spanning the region, wherein the span of such dimension extends from segments in the first group to segments in the second group. Correction so obtained by this process more readily preserves the intended electrical behavior of the original device design.
摘要翻译：公开了一种用于执行改进的光学邻近校正的方法，计算机程序产品和数据处理系统，其更好地尊重正在制造的设备的电气特性。本发明的优选实施例通过首先将掩模区域的周边划分成多个段来执行OPC，然后将段分组成至少两个不同的组，其中这些组中的第一组中的段被调整到适当位置，以便当模拟使用掩模的光刻时，最小化边缘放置误差（EPE）。第二组中的段被调整位置，以便最小化横跨该区域的维度的累积误差，其中这种维度的跨度从第一组中的段延伸到第二组中的段。通过该方法获得的校正更容易地保持原始设备设计的预期电气行为。

58. 发明授权

US08627244B2 Frequency domain layout decomposition in double patterning lithography 失效
标题翻译：双图案光刻中的频域布局分解
公开(公告)号：US08627244B2
公开(公告)日：2014-01-07
申请号：US13171513
申请日：2011-06-29
申请人： Kanak B. Agarwal , Shayak Banerjee
发明人： Kanak B. Agarwal , Shayak Banerjee
IPC分类号： G06F17/50
CPC分类号： G03F7/70466
摘要： A mechanism is provided for frequency domain layout decomposition in double pattern lithography (DPL) based on Fourier coefficient optimization (FCO). The Fourier transform of a layout represents the spatial frequency terms present in the layout. The mechanism models decomposed patterns for two exposures as a function of the corresponding Fourier coefficients. For each exposure, the mechanism sets the corresponding Fourier coefficients to zero for spatial frequency terms greater than the cut-off frequency of the optical system. The mechanism then optimizes non-zero Fourier coefficients for the two exposures to decompose the original target. The mechanism provides frequency domain optimization instead of conventional spatial domain methods, which naturally leads to optics-aware decomposition and stitch insertion in arbitrary two dimensional patterns.
摘要翻译：基于傅里叶系数优化（FCO）的双模式光刻（DPL）中的频域布局分解提供了一种机制。布局的傅里叶变换表示布局中存在的空间频率项。机制模型将两次曝光的分解模式作为相应的傅里叶系数的函数。对于每次曝光，机构将相应的傅立叶系数设置为零，以使空间频率项大于光学系统的截止频率。然后，该机制优化用于两次曝光的非零傅立叶系数以分解原始目标。该机制提供频域优化，而不是传统的空间域方法，这自然导致光学感知分解和针脚插入任意二维模式。

59. 发明授权

US08434033B2 Mask assignment for multiple patterning lithography 有权
标题翻译：多重图案平版印刷的掩模分配
公开(公告)号：US08434033B2
公开(公告)日：2013-04-30
申请号：US13223706
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G03F1/70 , G03F7/70466 , G03F7/70475
摘要： A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.
摘要翻译：提供了用于三重图案化光刻的掩模分配的机构。该机制通过设计规则相关的投影来识别尖端到尖端（TT），尖端到侧面（TS）以及侧向（SS）冲突部分。该机制分别查找TT，TS和SS冲突的针脚位置。机制颜色TT，TS和SS冲突部分与mask0 / mask1，mask0 / mask2，mask1 / mask2着色循环，每种类型分别着色。该机制使用现有的双向着色基础设施。作为第一个目标，该机制试图尽量减少冲突。作为第二个目的，该机构通过将针脚的两侧分配到相同的面罩来尝试最小化线迹数。一旦完成所有冲突部分的着色，该机制将颜色非冲突部分，以最大化曝光的最小重叠，并且如果双面是不同的颜色，则使用两种颜色，如果两面是相同颜色，则使用一种颜色。

60. 发明申请

US20130061183A1 Multiple Patterning Layout Decomposition for Ease of Conflict Removal 有权
标题翻译：多种图案化布局分解，易于冲突移除
公开(公告)号：US20130061183A1
公开(公告)日：2013-03-07
申请号：US13223844
申请日：2011-09-01
申请人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
发明人： Rani S. Abou Ghaida , Kanak B. Agarwal , Lars W. Liebmann , Sani R. Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction, The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features, The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.
摘要翻译：提供了一种用于具有冲突消除意识着色的多重图案化光刻的机构。该机制使得多个图案化着色意识到冲突移除开销。着色解决方案明确地将冲突移除的容易性作为着色目标之一。该机制预先计算出每个方向可以移动多少形状。机制生成一个冲突图，其中节点表示布局中的形状，边缘表示形状之间的冲突。该机制基于冲突特征之间可用的空间松弛来为边缘分配权重。然后，机构使用权重来引导多个图案化着色。该机制优先处理具有较高权重的冲突特征，以分配不同的颜色。

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