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51. 发明授权

US08912075B1 Wafer edge warp supression for thin wafer supported by tape frame 有权
标题翻译：用于由胶带框支撑的薄晶片的晶片边缘翘曲
公开(公告)号：US08912075B1
公开(公告)日：2014-12-16
申请号：US14265108
申请日：2014-04-29
申请人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/301 , H01L21/78 , H01L21/673 , H01L21/683
CPC分类号： H01L21/6836 , B32B3/266 , B32B37/0076 , B32B37/22 , B32B2307/202 , B32B2457/14 , H01L21/3065 , H01L21/3085 , H01L21/67092 , H01L21/67132 , H01L21/78 , H01L2221/68327 , H01L2221/6834
摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.
摘要翻译：对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。在一个示例中，减少支撑的半导体晶片中的边缘翘曲的方法包括将半导体晶片的背面粘附到包括安装在载带上方的带框架的基板载体的载带的内部。该方法还包括将粘合带粘附到半导体晶片的正面以及衬底载体的至少一部分。胶带包括露出半导体晶片正面的内部区域的开口。

52. 发明申请

US20140015109A1 METHOD OF DICED WAFER TRANSPORTATION 有权
标题翻译： DICED WAFER运输方法
公开(公告)号：US20140015109A1
公开(公告)日：2014-01-16
申请号：US13917973
申请日：2013-06-14
申请人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
发明人： Wei-Sheng Lei , Brad Eaton , Aparna Iyer , Saravjeet Singh , Todd Egan , Ajay Kumar , Seshadri Ramaswami
IPC分类号： H01L21/78
CPC分类号： H01L23/32 , H01L21/463 , H01L21/47 , H01L21/475 , H01L21/561 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/82 , H01L27/04 , H01L2924/0002 , H01L2924/00
摘要： Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape.
摘要翻译：描述了切割半导体晶片和输送单个模具的方法。在一个示例中，在其上划分具有多个集成电路的晶片的方法包括将晶片切割成设置在切割带上方的多个单片模具。该方法还涉及在切割胶带上方的多个分割模具之上和之间形成水溶性材料层。

53. 发明申请

US20120322237A1 LASER AND PLASMA ETCH WAFER DICING USING PHYSICALLY-REMOVABLE MASK 有权
标题翻译：激光和等离子体刻蚀使用物理可拆卸的面膜
公开(公告)号：US20120322237A1
公开(公告)日：2012-12-20
申请号：US13161036
申请日：2011-06-15
申请人： Wei-Sheng Lei , Saravjeet Singh , Madhava Rao Yalamanchili , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Saravjeet Singh , Madhava Rao Yalamanchili , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/78 , C23F1/08
CPC分类号： B23K26/40 , B23K26/0624 , B23K26/364 , B23K2103/172 , B23K2103/50 , H01L21/3081 , H01L21/31127 , H01L21/78
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。一种方法包括在半导体晶片上形成掩模。面罩覆盖并保护集成电路。用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。图案化使得集成电路之间的半导体晶片的区域露出。然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。然后将图案化掩模与单个集成电路分离。

54. 发明申请

US20120322236A1 WAFER DICING USING PULSE TRAIN LASER WITH MULTIPLE-PULSE BURSTS AND PLASMA ETCH 有权
标题翻译：使用多脉冲激光脉冲激光和等离子体蚀刻的脉冲激光
公开(公告)号：US20120322236A1
公开(公告)日：2012-12-20
申请号：US13161026
申请日：2011-06-15
申请人： Wei-Sheng Lei , Saravjeet Singh , Madhava Rao Yalamanchili , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Saravjeet Singh , Madhava Rao Yalamanchili , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/82 , C23F1/08
CPC分类号： H01L21/3086 , B23K26/06 , B23K26/0622 , B23K26/0624 , B23K26/0626 , B23K26/364 , B23K26/40 , B23K2103/172 , B23K2103/50 , H01L21/67207 , H01L21/78
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。一种方法包括在半导体晶片上形成掩模。掩模由覆盖和保护集成电路的层组成。使用多脉冲脉冲串的脉冲串激光划线方法对掩模进行构图，以提供具有间隙的图案化掩模。图案化使得集成电路之间的半导体晶片的区域露出。然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。

55. 发明申请

US20110312157A1 WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH 有权
标题翻译：使用基于FEMTOSECOND的激光和等离子体蚀刻的抛光
公开(公告)号：US20110312157A1
公开(公告)日：2011-12-22
申请号：US13160713
申请日：2011-06-15
申请人： Wei-Sheng Lei , Brad Eaton , Madhava Rao Yalamanchili , Saravjeet Singh , Ajay Kumar , James M. Holden
发明人： Wei-Sheng Lei , Brad Eaton , Madhava Rao Yalamanchili , Saravjeet Singh , Ajay Kumar , James M. Holden
IPC分类号： H01L21/822 , H01L21/3065 , H01L21/82
CPC分类号： H01L21/822 , B23K26/36 , H01J37/32889 , H01J37/32899 , H01L21/3065 , H01L21/3083 , H01L21/67069 , H01L21/67092 , H01L21/67207 , H01L21/6836 , H01L21/78 , H01L23/544 , H01L2221/68327 , H01L2924/0002 , H01L2924/00
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a femtosecond-based laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。一种方法包括在半导体晶片上形成掩模。掩模由覆盖和保护集成电路的层组成。使用基于飞秒的激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。图案化使得集成电路之间的半导体晶片的区域露出。然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。

56. 发明申请

US20160197015A1 HYBRID WAFER DICING APPROACH USING A POLYGON SCANNING-BASED LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS 审中-公开
标题翻译：使用基于多边形扫描的激光扫描过程和等离子体蚀刻过程的混合波形绘制方法
公开(公告)号：US20160197015A1
公开(公告)日：2016-07-07
申请号：US14589600
申请日：2015-01-05
申请人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/78 , H01L21/3065 , H01J37/32 , H01L21/02 , H01L21/67 , H01L21/268 , H01L21/308
CPC分类号： H01L21/78 , H01L21/0275 , H01L21/3086 , H01L21/67092 , H01L21/67207
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the plurality of integrated circuits. The mask is then patterned with a polygon scanning-based laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the plurality of integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the plurality of integrated circuits.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。在一个示例中，对具有多个集成电路的半导体晶片进行切割的方法包括在半导体晶片上形成掩模，该掩模由覆盖并保护多个集成电路的层构成。然后通过基于多边形扫描的激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露多个集成电路之间的半导体晶片的区域。然后通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对多个集成电路进行分割。

57. 发明授权

US09224650B2 Wafer dicing from wafer backside and front side 有权
标题翻译：从晶片背面和正面进行晶片切割
公开(公告)号：US09224650B2
公开(公告)日：2015-12-29
申请号：US14103534
申请日：2013-12-11
申请人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/00 , H01L21/46 , H01L21/30 , H01L21/78 , H01L21/308 , B23K26/32 , B23K26/36 , B23K26/40 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/78 , B23K26/32 , B23K26/364 , B23K26/40 , B23K26/402 , B23K2103/08 , B23K2103/172 , B23K2103/42 , B23K2103/50 , B23K2103/56 , H01L21/3081 , H01L21/31127 , H01L21/3213 , H01L21/6836 , H01L23/544 , H01L2221/68327 , H01L2221/6834 , H01L2223/54433 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： Approaches for backside laser scribe plus front side laser scribe and plasma etch dicing of a wafer or substrate are described. For example, a method of dicing a semiconductor wafer having a plurality of integrated circuits on a front side thereof and metallization on a backside thereof involves patterning the metallization on the backside with a first laser scribing process to provide a first plurality of laser scribe lines on the backside. The method also involves forming a mask on the front side. The method also involves patterning, from the front side, the mask with a second laser scribing process to provide a patterned mask with a second plurality of scribe lines exposing regions of the semiconductor wafer between the integrated circuits, wherein the second plurality of scribe lines is aligned with the first plurality of scribe lines. The method also involves plasma etching the semiconductor wafer through the second plurality of scribe lines to singulate the integrated circuits.
摘要翻译：描述了用于背面激光划片加正面激光划线和等离子体蚀刻切割晶片或衬底的方法。例如，在其前侧划分具有多个集成电路的半导体晶片的方法，其背面上的金属化包括用第一激光划线工艺在背面上图案化金属化，以在第一激光划线工艺上提供第一多个激光划线背面。该方法还涉及在前侧形成掩模。该方法还包括利用第二激光划线工艺从正面图案化掩模，以提供具有暴露在集成电路之间的半导体晶片的区域的第二多个划线的图案化掩模，其中第二多个划线是与第一组多个划线对准。该方法还包括通过第二多个划线对等离子体蚀刻半导体晶片以对集成电路进行分离。

58. 发明授权

US09112050B1 Dicing tape thermal management by wafer frame support ring cooling during plasma dicing 有权
标题翻译：切割胶带通过晶片框架进行热管理，支持等离子体切割期间的环形冷却
公开(公告)号：US09112050B1
公开(公告)日：2015-08-18
申请号：US14276683
申请日：2014-05-13
申请人： Wei-Sheng Lei , Prabhat Kumar , Brad Eaton , Ajay Kumar
发明人： Wei-Sheng Lei , Prabhat Kumar , Brad Eaton , Ajay Kumar
IPC分类号： H01L21/00 , H01L21/82 , H01L21/3065 , H01L21/67 , H01L21/78
CPC分类号： H01L21/82 , H01L21/3065 , H01L21/67 , H01L21/67069 , H01L21/67092 , H01L21/67109 , H01L21/67207 , H01L21/78
摘要： Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves introducing a substrate supported by a substrate carrier into a plasma etch chamber. The substrate has a patterned mask thereon covering integrated circuits and exposing streets of the substrate. The substrate carrier has a backside. The method also involves supporting at least a portion of the backside of the substrate carrier on a chuck of the plasma etch chamber. The method also involves cooling substantially all of the backside of the substrate carrier, the cooling involving cooling at least a first portion of the backside of the substrate carrier by the chuck. The method also involves plasma etching the substrate through the streets to singulate the integrated circuits while performing the cooling substantially all of the backside of the substrate carrier.
摘要翻译：对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。在一个实例中，对具有多个集成电路的半导体晶片进行切割的方法包括将由衬底载体支撑的衬底引入等离子体蚀刻室。衬底上具有图案化掩模，其覆盖集成电路并暴露衬底的街道。衬底载体具有背面。该方法还涉及将衬底载体的背侧的至少一部分支撑在等离子体蚀刻室的卡盘上。该方法还包括冷却基板载体的基本上所有背面，冷却涉及通过卡盘冷却基板载体的背面的至少第一部分。该方法还涉及通过街道等离子体蚀刻衬底以对集成电路进行单片化，同时基本上全部衬底载体的背面进行冷却。

59. 发明授权

US08912077B2 Hybrid laser and plasma etch wafer dicing using substrate carrier 有权
标题翻译：使用衬底载体的混合激光和等离子体蚀刻晶片切割
公开(公告)号：US08912077B2
公开(公告)日：2014-12-16
申请号：US13161052
申请日：2011-06-15
申请人： Saravjeet Singh , Brad Eaton , Ajay Kumar , Wei-Sheng Lei , James M. Holden , Madhava Rao Yalamanchili , Todd J. Egan
发明人： Saravjeet Singh , Brad Eaton , Ajay Kumar , Wei-Sheng Lei , James M. Holden , Madhava Rao Yalamanchili , Todd J. Egan
IPC分类号： H01L21/00
CPC分类号： H01L21/67069 , B23K26/0624 , B23K26/064 , B23K26/36 , B23K26/364 , B23K26/40 , B23K26/402 , B23K2103/172 , B23K2103/50 , H01L21/3065 , H01L21/3081 , H01L21/67092 , H01L21/67207 , H01L21/6836 , H01L21/68707 , H01L21/78 , H01L2221/68327 , H01L2221/68377
摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.
摘要翻译：对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。一种方法包括在半导体晶片上形成掩模，掩模由覆盖并保护集成电路的层组成。半导体晶片由衬底载体支撑。然后用激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。然后通过图案化掩模中的间隙蚀刻半导体晶片，以在由衬底载体支撑的同时对集成电路进行分离。

60. 发明申请

US20140363952A1 LASER, PLASMA ETCH, AND BACKSIDE GRIND PROCESS FOR WAFER DICING 审中-公开
标题翻译：激光，等离子体蚀刻和背面磨砂工艺
公开(公告)号：US20140363952A1
公开(公告)日：2014-12-11
申请号：US14466671
申请日：2014-08-22
申请人： Wei-Sheng Lei , Brad Eaton , Madhava Rao Yalamanchili , Saravjeet Singh , Ajay Kumar
发明人： Wei-Sheng Lei , Brad Eaton , Madhava Rao Yalamanchili , Saravjeet Singh , Ajay Kumar
IPC分类号： H01L21/78 , H01L21/02 , H01L21/027
CPC分类号： H01L21/78 , H01L21/02013 , H01L21/02016 , H01L21/02019 , H01L21/027 , Y10T29/5124
摘要： Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.
摘要翻译：执行前侧激光划线和等离子体蚀刻，然后进行背面研磨以分离集成电路芯片（IC）。形成覆盖在晶片上形成的IC的掩模，以及提供与IC的接口的任何凸块。通过激光划线将掩模图案化以提供具有间隙的图案化掩模。图案化使得半导体晶片的区域在形成IC的薄膜层之下露出。然后通过图案化掩模中的间隙蚀刻半导体晶片，以使蚀刻沟槽的前部部分地延伸穿过半导体晶片厚度。去除前侧面罩，施加到前侧的背面研磨带，和进行到蚀刻沟槽的后侧研磨，由此分离IC。

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