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51. 发明授权

US06747296B1 Avalanche photodiode multiplication region and avalanche photodiode with low impact ionization rate ratio 有权
标题翻译：雪崩光电二极管倍增区和雪崩光电二极管具有较低的电离离子化率
公开(公告)号：US06747296B1
公开(公告)日：2004-06-08
申请号：US10464693
申请日：2003-06-18
申请人： William Clark
发明人： William Clark
IPC分类号： H01L31072
CPC分类号： H01L31/107
摘要： An avalanche photodiode charge-carrier multiplication region comprises a first region fabricated from a first material having a first impact ionization threshold and a second region joined to the first region at an interface and fabricated from a second material having a second impact ionization threshold lower than the first impact ionization threshold. The first region includes, in the presence of an applied reverse-bias, first and second oppositely charged layers to establish an elevated, localized electric field within a sub-region of the first region. The first and second charged layers are arranged such that preferred charge carriers are accelerated by the localized electric field just prior to being injected into the second material where they impact ionize at predetermined statistical rate. Conversely, non-preferred charge carriers are accelerated by the localized electric field into the first material where, due to the higher impact ionization threshold of the first material, the non-preferred charge carriers impact ionize at a statistical rate lower than the statistical rate at which preferred charge carriers impact ionize in the second material.
摘要翻译：雪崩光电二极管电荷载体倍增区域包括由具有第一冲击电离阈值的第一材料制成的第一区域和在界面处接合到第一区域的第二区域，并由第二材料制成，第二材料具有低于第一冲击电离阈值。在施加的反向偏压的存在下，第一区域包括第一和第二相反电荷的层，以在第一区域的子区域内建立升高的局部电场。第一和第二带电层布置成使得优选的电荷载流子在刚被注入第二材料之前被局部电场加速，其中它们以预定的统计速率冲击电离。相反，非优选的载流子被局部电场加速到第一种材料中，其中由于第一材料的较高的电离电离阈值，非优选的载流子以低于统计率的统计率其中优选的电荷载体在第二种材料中碰撞电离。

52. 发明授权

US06400171B2 Method and system for processing integrated circuits 失效
标题翻译：集成电路处理方法及系统
公开(公告)号：US06400171B2
公开(公告)日：2002-06-04
申请号：US09273895
申请日：1999-03-22
申请人： Andres Bryant , William Clark , Edward J. Nowak , Minh Tong
发明人： Andres Bryant , William Clark , Edward J. Nowak , Minh Tong
IPC分类号： G01R3128
CPC分类号： G01R31/3004 , G01R31/2856
摘要： A circuit and a method for automatically detecting an operating condition of an integrated circuit chip and for automatically outputting a control signal in response to automatically detecting one of at least two said operating conditions. With the preferred embodiment, FET off currents are reduced during burn-in of a CMOS integrated chip. This is done by a compact, local sensing circuit. The sensing circuit is off during the normal chip operation, and the sensing circuit is only used where needed to provide a local signal to cut down excessive FET off currents. The sensing circuit preferred embodiment is designed with an NFET bandgap device that employs a novel layout approach.
摘要翻译：一种用于自动检测集成电路芯片的工作状态并响应于自动检测至少两个所述操作条件之一而自动输出控制信号的电路和方法。利用优选实施例，在CMOS集成芯片的老化期间，FET截止电流减小。这是通过紧凑的局部感测电路完成的。感测电路在正常芯片操作期间关闭，并且感测电路仅在需要时用于提供本地信号以减少过量的FET截止电流。感测电路优选实施例设计有采用新颖布局方法的NFET带隙器件。

53. 发明授权

US06303867B1 Shifted-plane core geometry cable 有权
标题翻译：移位平面核心几何电缆
公开(公告)号：US06303867B1
公开(公告)日：2001-10-16
申请号：US09650240
申请日：2000-08-29
申请人： William Clark , Joseph Dellagala , Kenneth Consalvo
发明人： William Clark , Joseph Dellagala , Kenneth Consalvo
IPC分类号： H01B1102
CPC分类号： H01B7/0823 , H01B7/0876
摘要： A telecommunications cable is disclosed in which a plurality of inwardly extending projections from the cable jacket, form a first and second plurality of substantially parallel longitudinal channels within the cable jacket. The first and second plurality of longitudinal channels are spaced apart from one another with respect to a reference line that transverses the cable, wherein the plurality of inwardly extending projections provide the spaced apart distance between the first plurality and the second plurality of longitudinally extending channels and between corresponding transmission media disposed within the first and second plurality of longitudinally extending channels. With this arrangement, cross talk between the transmission media within the cable is reduced and alien crosstalk between adjacently disposed or stacked cables is also reduced.
摘要翻译：公开了一种电信电缆，其中从电缆护套的多个向内延伸的突起形成电缆护套内的第一和第二多个基本平行的纵向通道。所述第一和第二多个纵向通道相对于穿过所述电缆的参考线彼此间隔开，其中所述多个向内延伸的突出部在所述第一多个纵向延伸的通道之间提供间隔开的距离，在布置在第一和第二多个纵向延伸通道内的相应的传输介质之间。通过这种布置，电缆内的传输介质之间的串扰减少，相邻布置或堆叠的电缆之间的异常串扰也减少。

54. 发明授权

US6162992A Shifted-plane core geometry cable 有权
标题翻译：移位平面核心几何电缆
公开(公告)号：US6162992A
公开(公告)日：2000-12-19
申请号：US274890
申请日：1999-03-23
申请人： William Clark , Joseph Dellagala , Kenneth Consalvo
发明人： William Clark , Joseph Dellagala , Kenneth Consalvo
IPC分类号： H01B7/08 , H01B11/02
CPC分类号： H01B7/0823 , H01B7/0876
摘要： A telecommunications cable is disclosed in which a plurality of inwardly extending projections from the cable jacket, form a first and second plurality of substantially parallel longitudinal channels within the cable jacket. The first and second plurality of longitudinal channels are spaced apart from one another with respect to a reference line that transverses the cable, wherein the plurality of inwardly extending projections provide the spaced apart distance between the first plurality and the second plurality of longitudinally extending channels and between corresponding transmission media disposed within the first and second plurality of longitudinally extending channels. With this arrangement, cross talk between the transmission media within the cable is reduced and alien crosstalk between adjacently disposed or stacked cables is also reduced.
摘要翻译：公开了一种电信电缆，其中从电缆护套的多个向内延伸的突起形成电缆护套内的第一和第二多个基本平行的纵向通道。所述第一和第二多个纵向通道相对于穿过所述电缆的参考线彼此间隔开，其中所述多个向内延伸的突出部在所述第一多个纵向延伸的通道之间提供间隔开的距离，在布置在第一和第二多个纵向延伸通道内的相应的传输介质之间。通过这种布置，电缆内的传输介质之间的串扰减少，相邻布置或堆叠的电缆之间的异常串扰也减少。

55. 发明授权

US09791398B2 Measurement device with sensor array 有权
公开(公告)号：US09791398B2
公开(公告)日：2017-10-17
申请号：US14343376
申请日：2012-09-06
申请人： William Clark , Sung Kwon Cho , Yuejun Zhao , Timothy J. Syciarz
发明人： William Clark , Sung Kwon Cho , Yuejun Zhao , Timothy J. Syciarz , R. Maxwell Flaherty , J. Christopher Flaherty , David W. Wagner
IPC分类号： G01N27/28 , G01N27/30 , B01L3/00 , G01N27/403 , G01N33/483
CPC分类号： G01N27/302 , B01L3/502738 , B01L2200/027 , B01L2200/0673 , B01L2300/0645 , B01L2300/0816 , B01L2300/0829 , B01L2300/087 , B01L2300/1827 , B01L2400/0406 , B01L2400/0427 , B01L2400/049 , B01L2400/0677 , G01N27/28 , G01N27/307 , G01N27/4035 , G01N33/4836
摘要： A system for obtaining a pH measurement includes a disposable probe and a reader. The disposable probe comprises multiple indicating electrodes and at least one reference electrode. The reader is configured to operably engage with the disposable probe and provide pH information of a sample.

56. 发明申请

US20080093634A1 SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD 有权
标题翻译：基于绝缘体的绝缘体辐射检测装置及方法
公开(公告)号：US20080093634A1
公开(公告)日：2008-04-24
申请号：US11960051
申请日：2007-12-19
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L31/119 , H01L31/18
CPC分类号： H01L29/78648
摘要： Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.
摘要翻译：公开了使用绝缘体上硅（SOI）技术检测电离辐射的结构和方法。在一个实施例中，本发明包括具有在衬底上形成的掩埋绝缘体层的衬底和形成在掩埋绝缘体层上的有源层。活性层可能完全耗尽。在有源层上形成晶体管，并且包括第一栅极导体，第一栅极电介质和源极/漏极扩散区。第一栅极导体可以包括具有基本（或完全）耗尽的掺杂浓度的材料，使得其具有比诸如本征多晶硅的掺杂多晶硅更高的电阻率。第二栅极导体形成在掩埋绝缘体层下方，并提供对应于第二栅极导体的第二栅极电介质。第一栅极导体和第二栅极导体之间的沟道区域由第二栅极导体（背栅极）控制，使得其作为辐射检测器。

57. 发明申请

US20070193769A1 DATA CABLE WITH CROSS-TWIST CABLED CORE PROFILE 有权
标题翻译：数据电缆与交叉电缆芯轮廓
公开(公告)号：US20070193769A1
公开(公告)日：2007-08-23
申请号：US11673357
申请日：2007-02-09
申请人： William Clark , Galen Gareis
发明人： William Clark , Galen Gareis
IPC分类号： H01B11/02
CPC分类号： H01B11/06
摘要： Cables including a plurality of twisted pairs of insulated conductors and a jacket surrounding the plurality of twisted pairs of insulated conductors, the jacket including a plurality of protrusions extending away from an inner circumferential surface of the jacket toward a center of the cable. The plurality of protrusions are configured so as to hold the plurality of twisted pairs away from the inner circumferential surface of the jacket, and may provide an air gap between the plurality of twisted pairs of insulated conductors and the inner circumferential surface of the jacket, thereby reducing susceptibility of the plurality of twisted pairs to alien near end crosstalk.
摘要翻译：电缆包括多个绝缘导体的双绞线和围绕多个绝缘导体的双绞线对的护套，所述护套包括多个突起，其从护套的内周表面朝着电缆的中心延伸。多个突起构造成将多个双绞线保持在远离夹套的内周面的状态，并且可以在绝缘导体的多个双绞线对与护套的内周面之间提供气隙，由此减少多个双绞线对外部近端串扰的敏感性。

58. 发明申请

US20070122957A1 LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES 有权
标题翻译：低功耗超低功耗，小型设备结构
公开(公告)号：US20070122957A1
公开(公告)日：2007-05-31
申请号：US11164651
申请日：2005-11-30
申请人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
IPC分类号： H01L21/8234 , H01L29/76 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.
摘要翻译：为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

59. 发明申请

US20070043456A1 Electronic device and method of representing an application or data using a shell application 审中-公开
标题翻译：使用shell应用程序表示应用程序或数据的电子设备和方法
公开(公告)号：US20070043456A1
公开(公告)日：2007-02-22
申请号：US10574239
申请日：2004-10-01
申请人： William Clark
发明人： William Clark
IPC分类号： G05B11/01 , G05B15/00
CPC分类号： G06F9/451
摘要： An electronic device (200) comprises a user interface (210) and a memory element (216), operably coupled to the user interface (210), which stores one or more files (applications or items of data) to be represented on the user interface. A processor (208) is operably coupled to the user interface (210) and memory element (216), and comprises a shell application (209) for representing the one or more files (217) on the user interface (210). The shell application (209) runs the executable code related to the one or more files (217) to provide to the user interface a representation of the one or more files (217) determined by the executable code. In this manner, a more useful and intuitive user interface is achieved as the shell representation of an application is able to provide a dynamic and context sensitive representation of itself.
摘要翻译：电子设备（200）包括可操作地耦合到用户接口（210）的用户界面（210）和存储元件（216），其存储要在用户上表示的一个或多个文件（应用或数据项）接口。处理器（208）可操作地耦合到用户接口（210）和存储器元件（216），并且包括用于表示用户界面（210）上的一个或多个文件（217）的外壳应用（209）。壳应用程序（209）运行与一个或多个文件（217）相关的可执行代码，以向用户界面提供由可执行代码确定的一个或多个文件（217）的表示。以这种方式，实现更有用和直观的用户界面，因为应用程序的shell表示能够提供自身的动态和上下文敏感表示。

60. 发明申请

US20060231881A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 有权
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20060231881A1
公开(公告)日：2006-10-19
申请号：US11427031
申请日：2006-06-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

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